]> git.sur5r.net Git - u-boot/blobdiff - arch/arm/dts/dra7.dtsi
arm: build some file(s) as ARM mode only
[u-boot] / arch / arm / dts / dra7.dtsi
index 8f1e25bcecbd76273f62671e8b9afa8f193ea261..e7fecf76564b989b1c733490ad84afbb654bbf2a 100644 (file)
@@ -41,6 +41,7 @@
                ethernet1 = &cpsw_emac1;
                d_can0 = &dcan1;
                d_can1 = &dcan2;
+               spi0 = &qspi;
        };
 
        timer {
                uart1: serial@4806a000 {
                        compatible = "ti,omap4-uart";
                        reg = <0x4806a000 0x100>;
+                       reg-shift = <2>;
                        interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
                        ti,hwmods = "uart1";
                        clock-frequency = <48000000>;
                uart2: serial@4806c000 {
                        compatible = "ti,omap4-uart";
                        reg = <0x4806c000 0x100>;
+                       reg-shift = <2>;
                        interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
                        ti,hwmods = "uart2";
                        clock-frequency = <48000000>;
                uart3: serial@48020000 {
                        compatible = "ti,omap4-uart";
                        reg = <0x48020000 0x100>;
+                       reg-shift = <2>;
                        interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
                        ti,hwmods = "uart3";
                        clock-frequency = <48000000>;
                uart4: serial@4806e000 {
                        compatible = "ti,omap4-uart";
                        reg = <0x4806e000 0x100>;
+                       reg-shift = <2>;
                        interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
                        ti,hwmods = "uart4";
                        clock-frequency = <48000000>;
                uart5: serial@48066000 {
                        compatible = "ti,omap4-uart";
                        reg = <0x48066000 0x100>;
+                       reg-shift = <2>;
                        interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
                        ti,hwmods = "uart5";
                        clock-frequency = <48000000>;
                uart6: serial@48068000 {
                        compatible = "ti,omap4-uart";
                        reg = <0x48068000 0x100>;
+                       reg-shift = <2>;
                        interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
                        ti,hwmods = "uart6";
                        clock-frequency = <48000000>;
                uart7: serial@48420000 {
                        compatible = "ti,omap4-uart";
                        reg = <0x48420000 0x100>;
+                       reg-shift = <2>;
                        interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
                        ti,hwmods = "uart7";
                        clock-frequency = <48000000>;
                uart8: serial@48422000 {
                        compatible = "ti,omap4-uart";
                        reg = <0x48422000 0x100>;
+                       reg-shift = <2>;
                        interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
                        ti,hwmods = "uart8";
                        clock-frequency = <48000000>;
                uart9: serial@48424000 {
                        compatible = "ti,omap4-uart";
                        reg = <0x48424000 0x100>;
+                       reg-shift = <2>;
                        interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
                        ti,hwmods = "uart9";
                        clock-frequency = <48000000>;
                uart10: serial@4ae2b000 {
                        compatible = "ti,omap4-uart";
                        reg = <0x4ae2b000 0x100>;
+                       reg-shift = <2>;
                        interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
                        ti,hwmods = "uart10";
                        clock-frequency = <48000000>;
 
                qspi: qspi@4b300000 {
                        compatible = "ti,dra7xxx-qspi";
-                       reg = <0x4b300000 0x100>;
-                       reg-names = "qspi_base";
+                       reg = <0x4b300000 0x100>,
+                             <0x5c000000 0x4000000>,
+                             <0x4a002558 0x4>;
+                       reg-names = "qspi_base", "qspi_mmap",
+                                   "qspi_ctrlmod";
                        #address-cells = <1>;
                        #size-cells = <0>;
                        ti,hwmods = "qspi";