ARM: dts: at91: sama5: Add the sfr node

[u-boot] / arch / arm / dts / dra72-evm-revc.dts

diff --git a/arch/arm/dts/dra72-evm-revc.dts b/arch/arm/dts/dra72-evm-revc.dts
index 0f8a7ef3c59c1cf72b81a3f6e119f6ee3a5bb8e2..bf588d00728d1973c3426f09421dc5c2bbb5bbe0 100644 (file)
--- a/arch/arm/dts/dra72-evm-revc.dts
+++ b/arch/arm/dts/dra72-evm-revc.dts
@@ -6,30 +6,51 @@
  * published by the Free Software Foundation.
  */
 #include "dra72-evm-common.dtsi"
+#include "dra72x-mmc-iodelay.dtsi"
 #include <dt-bindings/net/ti-dp83867.h>
 
 / {
        model = "TI DRA722 Rev C EVM";
 
-       memory {
+       memory@0 {
                device_type = "memory";
                reg = <0x0 0x80000000 0x0 0x80000000>; /* 2GB */
        };
-};
 
-&tps65917_regulators {
-       ldo2_reg: ldo2 {
-               /* LDO2_OUT --> VDDA_1V8_PHY2 */
-               regulator-name = "ldo2";
+       evm_1v8_sw: fixedregulator-evm_1v8 {
+               compatible = "regulator-fixed";
+               regulator-name = "evm_1v8";
                regulator-min-microvolt = <1800000>;
                regulator-max-microvolt = <1800000>;
+               vin-supply = <&smps4_reg>;
                regulator-always-on;
                regulator-boot-on;
        };
 };
 
+&i2c1 {
+       tps65917: tps65917@58 {
+               reg = <0x58>;
+
+               interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>;  /* IRQ_SYS_1N */
+       };
+};
+
+#include "dra72-evm-tps65917.dtsi"
+
+&ldo2_reg {
+       /* LDO2_OUT --> VDDA_1V8_PHY2 */
+       regulator-always-on;
+       regulator-boot-on;
+};
+
 &hdmi {
-       vdda_video-supply = <&ldo2_reg>;
+       vdda-supply = <&ldo2_reg>;
+};
+
+&pcf_gpio_21 {
+       interrupt-parent = <&gpio3>;
+       interrupts = <30 IRQ_TYPE_EDGE_FALLING>;
 };
 
 &mac {
@@ -40,13 +61,13 @@
 };
 
 &cpsw_emac0 {
-       phy-handle = <&dp83867_0>;
+       phy_id = <&davinci_mdio>, <2>;
        phy-mode = "rgmii-id";
        dual_emac_res_vlan = <1>;
 };
 
 &cpsw_emac1 {
-       phy-handle = <&dp83867_1>;
+       phy_id = <&davinci_mdio>, <3>;
        phy-mode = "rgmii-id";
        dual_emac_res_vlan = <2>;
 };
@@ -57,7 +78,10 @@
                ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
                ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
                ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
-               ti,min-output-imepdance;
+               ti,min-output-impedance;
+               interrupt-parent = <&gpio6>;
+               interrupts = <16 IRQ_TYPE_EDGE_FALLING>;
+               ti,dp83867-rxctrl-strap-quirk;
        };
 
        dp83867_1: ethernet-phy@3 {
@@ -65,6 +89,30 @@
                ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
                ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
                ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
-               ti,min-output-imepdance;
+               ti,min-output-impedance;
+               interrupt-parent = <&gpio6>;
+               interrupts = <16 IRQ_TYPE_EDGE_FALLING>;
+               ti,dp83867-rxctrl-strap-quirk;
        };
 };
+
+&mmc1 {
+       pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
+       pinctrl-0 = <&mmc1_pins_default>;
+       pinctrl-1 = <&mmc1_pins_hs>;
+       pinctrl-2 = <&mmc1_pins_sdr12>;
+       pinctrl-3 = <&mmc1_pins_sdr25>;
+       pinctrl-4 = <&mmc1_pins_sdr50>;
+       pinctrl-5 = <&mmc1_pins_ddr50_rev20 &mmc1_iodelay_ddr50_conf>;
+       pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev20_conf>;
+       vqmmc-supply = <&ldo1_reg>;
+};
+
+&mmc2 {
+       pinctrl-names = "default", "hs", "ddr_1_8v", "hs200_1_8v";
+       pinctrl-0 = <&mmc2_pins_default>;
+       pinctrl-1 = <&mmc2_pins_hs>;
+       pinctrl-2 = <&mmc2_pins_ddr_rev20 &mmc2_iodelay_ddr_conf>;
+       pinctrl-3 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_rev20_conf>;
+       vmmc-supply = <&evm_1v8_sw>;
+};