*/
/dts-v1/;
-/include/ "exynos54xx.dtsi"
+#include "exynos54xx.dtsi"
/ {
model = "Samsung/Google Peach Pit board based on Exynos5420";
"google,peach", "samsung,exynos5420", "samsung,exynos5";
config {
- google,bad-wake-gpios = <&gpio 0x56 0>; /* gpx0-6 */
+ google,bad-wake-gpios = <&gpx0 6 GPIO_ACTIVE_HIGH>;
hwid = "PIT TEST A-A 7848";
lazy-init = <1>;
};
mem-manuf = "samsung";
mem-type = "ddr3";
clock-frequency = <800000000>;
- arm-frequency = <1700000000>;
+ arm-frequency = <900000000>;
};
tmu@10060000 {
edp-lvds-bridge@48 {
compatible = "parade,ps8625";
reg = <0x48>;
+ sleep-gpio = <&gpx3 5 GPIO_ACTIVE_HIGH>;
+ reset-gpio = <&gpy7 7 GPIO_ACTIVE_HIGH>;
};
};
i2c@12e10000 { /* i2c9 */
clock-frequency = <400000>;
tpm@20 {
- compatible = "infineon,slb9645-tpm";
+ compatible = "infineon,slb9645tt";
reg = <0x20>;
};
};
spi@12d30000 { /* spi1 */
spi-max-frequency = <50000000>;
firmware_storage_spi: flash@0 {
+ compatible = "spi-flash";
reg = <0>;
/*
spi@12d40000 { /* spi2 */
spi-max-frequency = <4000000>;
spi-deactivate-delay = <200>;
- cros-ec@0 {
+
+ cros_ec: cros-ec@0 {
+ compatible = "google,cros-ec-spi";
reg = <0>;
- compatible = "google,cros-ec";
spi-half-duplex;
spi-max-timeout-ms = <1100>;
- spi-frame-header = <0xec>;
- ec-interrupt = <&gpio 93 1>; /* GPX1_5 */
+ ec-interrupt = <&gpx1 5 GPIO_ACTIVE_LOW>;
/*
* This describes the flash memory within the EC. Note
};
xhci@12000000 {
- samsung,vbus-gpio = <&gpio 0x40 0>; /* H00 */
+ samsung,vbus-gpio = <&gph0 0 GPIO_ACTIVE_HIGH>;
};
xhci@12400000 {
- samsung,vbus-gpio = <&gpio 0x41 0>; /* H01 */
+ samsung,vbus-gpio = <&gph0 1 GPIO_ACTIVE_HIGH>;
};
fimd@14400000 {
samsung,dual-lcd-enabled = <0>;
};
};
+
+#include "cros-ec-keyboard.dtsi"