Merge git://www.denx.de/git/u-boot-cfi-flash

[u-boot] / arch / arm / dts / fsl-ls1043a.dtsi

diff --git a/arch/arm/dts/fsl-ls1043a.dtsi b/arch/arm/dts/fsl-ls1043a.dtsi
index bf1dfe6db6177db53847393131417e4bab660aa8..fe6698f1612cc215c6fab72bb350b878ce2268fb 100644 (file)
--- a/arch/arm/dts/fsl-ls1043a.dtsi
+++ b/arch/arm/dts/fsl-ls1043a.dtsi
@@ -15,38 +15,6 @@
 / {
        compatible = "fsl,ls1043a";
        interrupt-parent = <&gic>;
-       cpus {
-               #address-cells = <2>;
-               #size-cells = <0>;
-
-               cpu0: cpu@0 {
-                       device_type = "cpu";
-                       compatible = "arm,cortex-a53";
-                       reg = <0x0 0x0>;
-                       clocks = <&clockgen 1 0>;
-               };
-
-               cpu1: cpu@1 {
-                       device_type = "cpu";
-                       compatible = "arm,cortex-a53";
-                       reg = <0x0 0x1>;
-                       clocks = <&clockgen 1 0>;
-               };
-
-               cpu2: cpu@2 {
-                       device_type = "cpu";
-                       compatible = "arm,cortex-a53";
-                       reg = <0x0 0x2>;
-                       clocks = <&clockgen 1 0>;
-               };
-
-               cpu3: cpu@3 {
-                       device_type = "cpu";
-                       compatible = "arm,cortex-a53";
-                       reg = <0x0 0x3>;
-                       clocks = <&clockgen 1 0>;
-               };
-       };
 
        sysclk: sysclk {
                compatible = "fixed-clock";
@@ -247,5 +215,72 @@
                        big-endian;
                        status = "disabled";
                };
+
+               usb0: usb3@2f00000 {
+                       compatible = "fsl,layerscape-dwc3";
+                       reg = <0x0 0x2f00000 0x0 0x10000>;
+                       interrupts = <0 60 0x4>;
+                       dr_mode = "host";
+               };
+
+               usb1: usb3@3000000 {
+                       compatible = "fsl,layerscape-dwc3";
+                       reg = <0x0 0x3000000 0x0 0x10000>;
+                       interrupts = <0 61 0x4>;
+                       dr_mode = "host";
+               };
+
+               usb2: usb3@3100000 {
+                       compatible = "fsl,layerscape-dwc3";
+                       reg = <0x0 0x3100000 0x0 0x10000>;
+                       interrupts = <0 63 0x4>;
+                       dr_mode = "host";
+               };
+
+               pcie@3400000 {
+                       compatible = "fsl,ls-pcie", "snps,dw-pcie";
+                       reg = <0x00 0x03400000 0x0 0x10000   /* dbi registers */
+                              0x00 0x03410000 0x0 0x10000   /* lut registers */
+                              0x40 0x00000000 0x0 0x20000>; /* configuration space */
+                       reg-names = "dbi", "lut", "config";
+                       big-endian;
+                       #address-cells = <3>;
+                       #size-cells = <2>;
+                       device_type = "pci";
+                       bus-range = <0x0 0xff>;
+                       ranges = <0x81000000 0x0 0x00000000 0x40 0x00020000 0x0 0x00010000   /* downstream I/O */
+                                 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+               };
+
+               pcie@3500000 {
+                       compatible = "fsl,ls-pcie", "snps,dw-pcie";
+                       reg = <0x00 0x03500000 0x0 0x10000   /* dbi registers */
+                              0x00 0x03510000 0x0 0x10000   /* lut registers */
+                              0x48 0x00000000 0x0 0x20000>; /* configuration space */
+                       reg-names = "dbi", "lut", "config";
+                       big-endian;
+                       #address-cells = <3>;
+                       #size-cells = <2>;
+                       device_type = "pci";
+                       num-lanes = <2>;
+                       bus-range = <0x0 0xff>;
+                       ranges = <0x81000000 0x0 0x00000000 0x48 0x00020000 0x0 0x00010000   /* downstream I/O */
+                                 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+               };
+
+               pcie@3600000 {
+                       compatible = "fsl,ls-pcie", "snps,dw-pcie";
+                       reg = <0x00 0x03600000 0x0 0x10000   /* dbi registers */
+                              0x00 0x03610000 0x0 0x10000   /* lut registers */
+                              0x50 0x00000000 0x0 0x20000>; /* configuration space */
+                       reg-names = "dbi", "lut", "config";
+                       big-endian;
+                       #address-cells = <3>;
+                       #size-cells = <2>;
+                       device_type = "pci";
+                       bus-range = <0x0 0xff>;
+                       ranges = <0x81000000 0x0 0x00000000 0x50 0x00020000 0x0 0x00010000   /* downstream I/O */
+                                 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+               };
        };
 };