enet2_rgmii_phy = &rgmii_phy3;
enet0_sgmii_phy = &sgmii_phy1c;
enet1_sgmii_phy = &sgmii_phy1d;
+ spi0 = &qspi;
+ spi1 = &dspi0;
};
};
dspiflash: at45db021d@0 {
#address-cells = <1>;
#size-cells = <1>;
- compatible = "atmel,at45db021d", "atmel,at45", "atmel,dataflash";
+ compatible = "atmel,dataflash";
spi-max-frequency = <16000000>;
spi-cpol;
spi-cpha;
};
};
+&qspi {
+ bus-num = <0>;
+ status = "okay";
+
+ qflash0: s25fl128s@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash";
+ spi-max-frequency = <20000000>;
+ reg = <0>;
+ };
+};
+
&i2c0 {
status = "okay";