Merge git://www.denx.de/git/u-boot-cfi-flash

[u-boot] / arch / arm / dts / meson-gxbb.dtsi

diff --git a/arch/arm/dts/meson-gxbb.dtsi b/arch/arm/dts/meson-gxbb.dtsi
index 39a774ad83ce13c246bbf8ea417e8c904fd10bdb..86105a69690aa8c66342e7e22e6846a6140203cb 100644 (file)
--- a/arch/arm/dts/meson-gxbb.dtsi
+++ b/arch/arm/dts/meson-gxbb.dtsi
@@ -97,17 +97,6 @@
        };
 };
 
-&cbus {
-       spifc: spi@8c80 {
-               compatible = "amlogic,meson-gxbb-spifc";
-               reg = <0x0 0x08c80 0x0 0x80>;
-               #address-cells = <1>;
-               #size-cells = <0>;
-               clocks = <&clkc CLKID_SPI>;
-               status = "disabled";
-       };
-};
-
 &ethmac {
        clocks = <&clkc CLKID_ETH>,
                 <&clkc CLKID_FCLK_DIV2>,
@@ -129,6 +118,7 @@
                        reg-names = "mux", "pull", "gpio";
                        gpio-controller;
                        #gpio-cells = <2>;
+                       gpio-ranges = <&pinctrl_aobus 0 0 14>;
                };
 
                uart_ao_a_pins: uart_ao_a {
@@ -203,30 +193,62 @@
                                function = "pwm_ao_b";
                        };
                };
-       };
 
-       clkc_AO: clock-controller@040 {
-               compatible = "amlogic,gxbb-aoclkc";
-               reg = <0x0 0x00040 0x0 0x4>;
-               #clock-cells = <1>;
-               #reset-cells = <1>;
-       };
+               i2s_am_clk_pins: i2s_am_clk {
+                       mux {
+                               groups = "i2s_am_clk";
+                               function = "i2s_out_ao";
+                       };
+               };
 
-       pwm_ab_AO: pwm@550 {
-               compatible = "amlogic,meson-gxbb-pwm";
-               reg = <0x0 0x0550 0x0 0x10>;
-               #pwm-cells = <3>;
-               status = "disabled";
-       };
+               i2s_out_ao_clk_pins: i2s_out_ao_clk {
+                       mux {
+                               groups = "i2s_out_ao_clk";
+                               function = "i2s_out_ao";
+                       };
+               };
+
+               i2s_out_lr_clk_pins: i2s_out_lr_clk {
+                       mux {
+                               groups = "i2s_out_lr_clk";
+                               function = "i2s_out_ao";
+                       };
+               };
+
+               i2s_out_ch01_ao_pins: i2s_out_ch01_ao {
+                       mux {
+                               groups = "i2s_out_ch01_ao";
+                               function = "i2s_out_ao";
+                       };
+               };
+
+               i2s_out_ch23_ao_pins: i2s_out_ch23_ao {
+                       mux {
+                               groups = "i2s_out_ch23_ao";
+                               function = "i2s_out_ao";
+                       };
+               };
+
+               i2s_out_ch45_ao_pins: i2s_out_ch45_ao {
+                       mux {
+                               groups = "i2s_out_ch45_ao";
+                               function = "i2s_out_ao";
+                       };
+               };
+
+               spdif_out_ao_6_pins: spdif_out_ao_6 {
+                       mux {
+                               groups = "spdif_out_ao_6";
+                               function = "spdif_out_ao";
+                       };
+               };
 
-       i2c_AO: i2c@500 {
-               compatible = "amlogic,meson-gxbb-i2c";
-               reg = <0x0 0x500 0x0 0x20>;
-               interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>;
-               clocks = <&clkc CLKID_AO_I2C>;
-               #address-cells = <1>;
-               #size-cells = <0>;
-               status = "disabled";
+               spdif_out_ao_13_pins: spdif_out_ao_13 {
+                       mux {
+                               groups = "spdif_out_ao_13";
+                               function = "spdif_out_ao";
+                       };
+               };
        };
 };
 
@@ -245,6 +267,7 @@
                        reg-names = "mux", "pull", "pull-enable", "gpio";
                        gpio-controller;
                        #gpio-cells = <2>;
+                       gpio-ranges = <&pinctrl_periphs 0 14 120>;
                };
 
                emmc_pins: emmc {
@@ -467,6 +490,34 @@
                                function = "hdmi_i2c";
                        };
                };
+
+               i2sout_ch23_y_pins: i2sout_ch23_y {
+                       mux {
+                               groups = "i2sout_ch23_y";
+                               function = "i2s_out";
+                       };
+               };
+
+               i2sout_ch45_y_pins: i2sout_ch45_y {
+                       mux {
+                               groups = "i2sout_ch45_y";
+                               function = "i2s_out";
+                       };
+               };
+
+               i2sout_ch67_y_pins: i2sout_ch67_y {
+                       mux {
+                               groups = "i2sout_ch67_y";
+                               function = "i2s_out";
+                       };
+               };
+
+               spdif_out_y_pins: spdif_out_y {
+                       mux {
+                               groups = "spdif_out_y";
+                               function = "spdif_out";
+                       };
+               };
        };
 };
 
@@ -478,10 +529,51 @@
        };
 };
 
+&apb {
+       mali: gpu@c0000 {
+               compatible = "amlogic,meson-gxbb-mali", "arm,mali-450";
+               reg = <0x0 0xc0000 0x0 0x40000>;
+               interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-names = "gp", "gpmmu", "pp", "pmu",
+                       "pp0", "ppmmu0", "pp1", "ppmmu1",
+                       "pp2", "ppmmu2";
+               clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;
+               clock-names = "bus", "core";
+
+               /*
+                * Mali clocking is provided by two identical clock paths
+                * MALI_0 and MALI_1 muxed to a single clock by a glitch
+                * free mux to safely change frequency while running.
+                */
+               assigned-clocks = <&clkc CLKID_MALI_0_SEL>,
+                                 <&clkc CLKID_MALI_0>,
+                                 <&clkc CLKID_MALI>; /* Glitch free mux */
+               assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
+                                        <0>, /* Do Nothing */
+                                        <&clkc CLKID_MALI_0>;
+               assigned-clock-rates = <0>, /* Do Nothing */
+                                      <666666666>,
+                                      <0>; /* Do Nothing */
+       };
+};
+
 &i2c_A {
        clocks = <&clkc CLKID_I2C>;
 };
 
+&i2c_AO {
+       clocks = <&clkc CLKID_AO_I2C>;
+};
+
 &i2c_B {
        clocks = <&clkc CLKID_I2C>;
 };
@@ -490,6 +582,16 @@
        clocks = <&clkc CLKID_I2C>;
 };
 
+&saradc {
+       compatible = "amlogic,meson-gxbb-saradc", "amlogic,meson-saradc";
+       clocks = <&xtal>,
+                <&clkc CLKID_SAR_ADC>,
+                <&clkc CLKID_SANA>,
+                <&clkc CLKID_SAR_ADC_CLK>,
+                <&clkc CLKID_SAR_ADC_SEL>;
+       clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel";
+};
+
 &sd_emmc_a {
        clocks = <&clkc CLKID_SD_EMMC_A>,
                 <&xtal>,
@@ -511,6 +613,27 @@
        clock-names = "core", "clkin0", "clkin1";
 };
 
+&spifc {
+       clocks = <&clkc CLKID_SPI>;
+};
+
 &vpu {
        compatible = "amlogic,meson-gxbb-vpu", "amlogic,meson-gx-vpu";
 };
+
+&hwrng {
+       clocks = <&clkc CLKID_RNG0>;
+       clock-names = "core";
+};
+
+&hdmi_tx {
+       compatible = "amlogic,meson-gxbb-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
+       resets = <&reset RESET_HDMITX_CAPB3>,
+                <&reset RESET_HDMI_SYSTEM_RESET>,
+                <&reset RESET_HDMI_TX>;
+       reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
+       clocks = <&clkc CLKID_HDMI_PCLK>,
+                <&clkc CLKID_CLK81>,
+                <&clkc CLKID_GCLK_VENCI_INT0>;
+       clock-names = "isfr", "iahb", "venci";
+};