tegra: video: Move LCD driver to use the DM PWM driver

[u-boot] / arch / arm / dts / rk3288.dtsi

diff --git a/arch/arm/dts/rk3288.dtsi b/arch/arm/dts/rk3288.dtsi
index 6b5145cc6d304144ea7d1af7650848afe57b0d88..e51c75c150c6b8c7e940f108123f7ffea9d2e8f1 100644 (file)
--- a/arch/arm/dts/rk3288.dtsi
+++ b/arch/arm/dts/rk3288.dtsi
@@ -16,6 +16,15 @@
 
        interrupt-parent = <&gic>;
        aliases {
+               gpio0 = &gpio0;
+               gpio1 = &gpio1;
+               gpio2 = &gpio2;
+               gpio3 = &gpio3;
+               gpio4 = &gpio4;
+               gpio5 = &gpio5;
+               gpio6 = &gpio6;
+               gpio7 = &gpio7;
+               gpio8 = &gpio8;
                i2c0 = &i2c0;
                i2c1 = &i2c1;
                i2c2 = &i2c2;
@@ -315,6 +324,7 @@
                interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
                reg-shift = <2>;
                reg-io-width = <4>;
+               clock-frequency = <24000000>;
                clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
                clock-names = "baudclk", "apb_pclk";
                pinctrl-names = "default";
@@ -328,6 +338,7 @@
                interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
                reg-shift = <2>;
                reg-io-width = <4>;
+               clock-frequency = <24000000>;
                clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
                clock-names = "baudclk", "apb_pclk";
                pinctrl-names = "default";
@@ -341,6 +352,7 @@
                interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
                reg-shift = <2>;
                reg-io-width = <4>;
+               clock-frequency = <24000000>;
                clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
                clock-names = "baudclk", "apb_pclk";
                pinctrl-names = "default";
@@ -353,6 +365,7 @@
                interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
                reg-shift = <2>;
                reg-io-width = <4>;
+               clock-frequency = <24000000>;
                clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
                clock-names = "baudclk", "apb_pclk";
                pinctrl-names = "default";
@@ -366,6 +379,7 @@
                interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
                reg-shift = <2>;
                reg-io-width = <4>;
+               clock-frequency = <24000000>;
                clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
                clock-names = "baudclk", "apb_pclk";
                pinctrl-names = "default";
@@ -454,6 +468,7 @@
        };
 
        dmc: dmc@ff610000 {
+               u-boot,dm-pre-reloc;
                compatible = "rockchip,rk3288-dmc", "syscon";
                rockchip,cru = <&cru>;
                rockchip,grf = <&grf>;
@@ -569,11 +584,13 @@
        };
 
        pmu: power-management@ff730000 {
+               u-boot,dm-pre-reloc;
                compatible = "rockchip,rk3288-pmu", "syscon";
                reg = <0xff730000 0x100>;
        };
 
        sgrf: syscon@ff740000 {
+               u-boot,dm-pre-reloc;
                compatible = "rockchip,rk3288-sgrf", "syscon";
                reg = <0xff740000 0x1000>;
        };
@@ -582,6 +599,7 @@
                compatible = "rockchip,rk3288-cru";
                reg = <0xff760000 0x1000>;
                rockchip,grf = <&grf>;
+               u-boot,dm-pre-reloc;
                #clock-cells = <1>;
                #reset-cells = <1>;
                assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>,
@@ -600,6 +618,7 @@
        };
 
        grf: syscon@ff770000 {
+               u-boot,dm-pre-reloc;
                compatible = "rockchip,rk3288-grf", "syscon";
                reg = <0xff770000 0x1000>;
        };
@@ -612,6 +631,21 @@
                status = "disabled";
        };
 
+       spdif: sound@ff88b0000 {
+               compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif";
+               reg = <0xff8b0000 0x10000>;
+               #sound-dai-cells = <0>;
+               clock-names = "hclk", "mclk";
+               clocks = <&cru HCLK_SPDIF8CH>, <&cru SCLK_SPDIF8CH>;
+               dmas = <&dmac_bus_s 3>;
+               dma-names = "tx";
+               interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&spdif_tx>;
+               rockchip,grf = <&grf>;
+               status = "disabled";
+       };
+
        i2s: i2s@ff890000 {
                compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
                reg = <0xff890000 0x10000>;
@@ -673,6 +707,7 @@
                iommus = <&vopl_mmu>;
                power-domains = <&power RK3288_PD_VIO>;
                status = "disabled";
+               u-boot,dm-pre-reloc;
                vopl_out: port {
                        #address-cells = <1>;
                        #size-cells = <0>;
@@ -804,6 +839,7 @@
        };
 
        noc: syscon@ffac0000 {
+               u-boot,dm-pre-reloc;
                compatible = "rockchip,rk3288-noc", "syscon";
                reg = <0xffac0000 0x2000>;
        };
@@ -1396,6 +1432,12 @@
                                                <4 3 3 &pcfg_pull_none>;
                        };
                };
+
+               spdif {
+                       spdif_tx: spdif-tx {
+                               rockchip,pins = <RK_GPIO6 11 RK_FUNC_1 &pcfg_pull_none>;
+                       };
+               };
        };
 
        power: power-controller {