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[u-boot] / arch / arm / dts / rk3399.dtsi

diff --git a/arch/arm/dts/rk3399.dtsi b/arch/arm/dts/rk3399.dtsi
index bafa40a1f92be06552b212719336eeb2afd7891b..83c257b1228bd0b7b791040e603b2ac67f06e5b1 100644 (file)
--- a/arch/arm/dts/rk3399.dtsi
+++ b/arch/arm/dts/rk3399.dtsi
@@ -1,7 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd.
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <dt-bindings/clock/rk3399-cru.h>
@@ -1402,6 +1401,116 @@
                status = "disabled";
        };
 
+       vopl: vop@ff8f0000 {
+               u-boot,dm-pre-reloc;
+               compatible = "rockchip,rk3399-vop-lit";
+               reg = <0x0 0xff8f0000 0x0 0x3efc>;
+               interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
+               clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
+               clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
+               resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
+               reset-names = "axi", "ahb", "dclk";
+               status = "disabled";
+               vopl_out: port {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       vopl_out_mipi: endpoint@0 {
+                               reg = <3>;
+                               remote-endpoint = <&mipi_in_vopl>;
+                       };
+
+                       vopl_out_hdmi: endpoint@1 {
+                               reg = <1>;
+                               remote-endpoint = <&hdmi_in_vopl>;
+                       };
+               };
+       };
+
+       vopb: vop@ff900000 {
+               u-boot,dm-pre-reloc;
+               compatible = "rockchip,rk3399-vop-big";
+               reg = <0x0 0xff900000 0x0 0x3efc>;
+               interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
+               clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
+               #clock-cells = <0>;
+               clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
+               resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
+               reset-names = "axi", "ahb", "dclk";
+               status = "disabled";
+               vopb_out: port {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       vopb_out_mipi: endpoint@0 {
+                               reg = <3>;
+                               remote-endpoint = <&mipi_in_vopb>;
+                       };
+
+                       vopb_out_hdmi: endpoint@1 {
+                               reg = <1>;
+                               remote-endpoint = <&hdmi_in_vopb>;
+                       };
+               };
+       };
+
+       hdmi: hdmi@ff940000 {
+               compatible = "rockchip,rk3399-dw-hdmi";
+               reg = <0x0 0xff940000 0x0 0x20000>;
+               reg-io-width = <4>;
+               rockchip,grf = <&grf>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&hdmi_i2c_xfer>;
+               power-domains = <&power RK3399_PD_HDCP>;
+               interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>;
+               clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_SFR>, <&cru PLL_VPLL>, <&cru PCLK_VIO_GRF>;
+               clock-names = "iahb", "isfr", "vpll", "grf";
+               status = "disabled";
+
+               ports {
+                       hdmi_in: port {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               hdmi_in_vopb: endpoint@0 {
+                                       reg = <0>;
+                                       remote-endpoint = <&vopb_out_hdmi>;
+                               };
+                               hdmi_in_vopl: endpoint@1 {
+                                       reg = <1>;
+                                       remote-endpoint = <&vopl_out_hdmi>;
+                               };
+                       };
+               };
+       };
+
+       mipi_dsi: mipi@ff960000 {
+               compatible = "rockchip,rk3399_mipi_dsi";
+               reg = <0x0 0xff960000 0x0 0x8000>;
+               interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>;
+               clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>,
+                        <&cru SCLK_DPHY_TX0_CFG>;
+               clock-names = "ref", "pclk", "phy_cfg";
+               rockchip,grf = <&grf>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               status = "disabled";
+               ports {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       reg = <1>;
+                       mipi_in: port {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               mipi_in_vopb: endpoint@0 {
+                                       reg = <0>;
+                                       remote-endpoint = <&vopb_out_mipi>;
+                               };
+                               mipi_in_vopl: endpoint@1 {
+                                       reg = <1>;
+                                       remote-endpoint = <&vopl_out_mipi>;
+                               };
+                       };
+               };
+       };
+
        pinctrl: pinctrl {
                u-boot,dm-pre-reloc;
                compatible = "rockchip,rk3399-pinctrl";