timer1 = &timer1;
timer2 = &timer2;
timer3 = &timer3;
+ spi0 = &qspi;
+ spi1 = &spi0;
+ spi2 = &spi1;
+ mmc = &mmc;
};
cpus {
interrupts = <0 151 4>;
clocks = <&qspi_clk>;
ext-decoder = <0>; /* external decoder */
- num-chipselect = <4>;
+ num-cs = <4>;
fifo-depth = <128>;
+ sram-size = <128>;
bus-num = <2>;
status = "disabled";
};
#size-cells = <0>;
reg = <0xfff00000 0x1000>;
interrupts = <0 154 4>;
- num-chipselect = <4>;
+ num-cs = <4>;
bus-num = <0>;
tx-dma-channel = <&pdma 16>;
rx-dma-channel = <&pdma 17>;
#size-cells = <0>;
reg = <0xfff01000 0x1000>;
interrupts = <0 156 4>;
- num-chipselect = <4>;
+ num-cs = <4>;
bus-num = <1>;
tx-dma-channel = <&pdma 20>;
rx-dma-channel = <&pdma 21>;