arm: socfpga: scan: Staticize scan_mgr_io_scan_chain_prg()

[u-boot] / arch / arm / dts / socfpga.dtsi

diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi
index 4472fd92685c4b84d54e9dfb0041646f709e3477..e17e9f4a3ca8807fa401d18613244465e260ae17 100644 (file)
--- a/arch/arm/dts/socfpga.dtsi
+++ b/arch/arm/dts/socfpga.dtsi
@@ -1,18 +1,7 @@
 /*
  *  Copyright (C) 2012 Altera <www.altera.com>
  *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include "skeleton.dtsi"
@@ -31,6 +20,10 @@
                timer1 = &timer1;
                timer2 = &timer2;
                timer3 = &timer3;
+               spi0 = &qspi;
+               spi1 = &spi0;
+               spi2 = &spi1;
+               mmc = &mmc;
        };
 
        cpus {
@@ -639,6 +632,50 @@
                        clock-names = "biu", "ciu";
                };
 
+               qspi: spi@ff705000 {
+                       compatible = "cadence,qspi";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       reg = <0xff705000 0x1000>,
+                               <0xffa00000 0x1000>;
+                       interrupts = <0 151 4>;
+                       clocks = <&qspi_clk>;
+                       ext-decoder = <0>;  /* external decoder */
+                       num-cs = <4>;
+                       fifo-depth = <128>;
+                       sram-size = <128>;
+                       bus-num = <2>;
+                       status = "disabled";
+               };
+
+               spi0: spi@fff00000 {
+                       compatible = "snps,dw-apb-ssi";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       reg = <0xfff00000 0x1000>;
+                       interrupts = <0 154 4>;
+                       num-cs = <4>;
+                       bus-num = <0>;
+                       tx-dma-channel = <&pdma 16>;
+                       rx-dma-channel = <&pdma 17>;
+                       clocks = <&per_base_clk>;
+                       status = "disabled";
+               };
+
+               spi1: spi@fff01000 {
+                       compatible = "snps,dw-apb-ssi";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       reg = <0xfff01000 0x1000>;
+                       interrupts = <0 156 4>;
+                       num-cs = <4>;
+                       bus-num = <1>;
+                       tx-dma-channel = <&pdma 20>;
+                       rx-dma-channel = <&pdma 21>;
+                       clocks = <&per_base_clk>;
+                       status = "disabled";
+               };
+
                /* Local timer */
                timer@fffec600 {
                        compatible = "arm,cortex-a9-twd-timer";