ARM: socfpga: Synchronize Arria10 SoCDK SDMMC handoff

[u-boot] / arch / arm / dts / socfpga_cyclone5_is1.dts

diff --git a/arch/arm/dts/socfpga_cyclone5_is1.dts b/arch/arm/dts/socfpga_cyclone5_is1.dts
index 2e2b71fefb6c4771b0f4b98741f9eb4e2e541e74..aa1ce2c3e2e6e2062d73b34099bfe4397b70e249 100644 (file)
--- a/arch/arm/dts/socfpga_cyclone5_is1.dts
+++ b/arch/arm/dts/socfpga_cyclone5_is1.dts
@@ -1,7 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  *  Copyright (C) 2012 Altera Corporation <www.altera.com>
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include "socfpga_cyclone5.dtsi"
@@ -87,7 +86,7 @@
                u-boot,dm-pre-reloc;
                #address-cells = <1>;
                #size-cells = <1>;
-               compatible = "n25q00";
+               compatible = "n25q00", "spi-flash";
                reg = <0>;      /* chip select */
                spi-max-frequency = <100000000>;
                m25p,fast-read;