arm: socfpga: fix qspi flash compatible (add "spi-flash")

[u-boot] / arch / arm / dts / socfpga_cyclone5_socdk.dts

diff --git a/arch/arm/dts/socfpga_cyclone5_socdk.dts b/arch/arm/dts/socfpga_cyclone5_socdk.dts
index a202709d6030b06760669115b4aba931fa810988..3af51134bbec6c5e97951641cf005541cc1ca0ab 100644 (file)
--- a/arch/arm/dts/socfpga_cyclone5_socdk.dts
+++ b/arch/arm/dts/socfpga_cyclone5_socdk.dts
@@ -21,7 +21,7 @@
        };
 
        aliases {
-               /* this allow the ethaddr uboot environmnet variable contents
+               /* this allow the ethaddr uboot environment variable contents
                 * to be added to the gmac1 device tree blob.
                 */
                ethernet0 = &gmac1;
@@ -54,10 +54,18 @@
        rxc-skew-ps = <2000>;
 };
 
+&gpio0 {
+       status = "okay";
+};
+
 &gpio1 {
        status = "okay";
 };
 
+&gpio2 {
+       status = "okay";
+};
+
 &i2c0 {
        status = "okay";
 
@@ -84,21 +92,22 @@
 
 &qspi {
        status = "okay";
+       u-boot,dm-pre-reloc;
 
        flash0: n25q00@0 {
+               u-boot,dm-pre-reloc;
                #address-cells = <1>;
                #size-cells = <1>;
-               compatible = "n25q00";
+               compatible = "n25q00", "spi-flash";
                reg = <0>;      /* chip select */
                spi-max-frequency = <100000000>;
                m25p,fast-read;
                page-size = <256>;
                block-size = <16>; /* 2^16, 64KB */
-               read-delay = <4>;  /* delay value in read data capture register */
-               tshsl-ns = <50>;
-               tsd2d-ns = <50>;
-               tchsh-ns = <4>;
-               tslch-ns = <4>;
+               cdns,tshsl-ns = <50>;
+               cdns,tsd2d-ns = <50>;
+               cdns,tchsh-ns = <4>;
+               cdns,tslch-ns = <4>;
        };
 };