Merge branch 'rmobile' of git://git.denx.de/u-boot-sh

[u-boot] / arch / arm / dts / stm32f746.dtsi

diff --git a/arch/arm/dts/stm32f746.dtsi b/arch/arm/dts/stm32f746.dtsi
index afcd3277c5bd0a40d2ad97de96f79046e78f3684..783d4e734e5873f428d6f3a992d2fde24d68a388 100644 (file)
--- a/arch/arm/dts/stm32f746.dtsi
+++ b/arch/arm/dts/stm32f746.dtsi
@@ -1,5 +1,6 @@
 /*
  * Copyright 2016 - Michael Kurz <michi.kurz@gmail.com>
+ * Copyright 2016 - Vikas MANOCHA <vikas.manocha@st.com>
  *
  * Based on:
  * stm32f429.dtsi from Linux
@@ -46,6 +47,8 @@
 
 #include "armv7-m.dtsi"
 #include <dt-bindings/pinctrl/stm32f746-pinfunc.h>
+#include <dt-bindings/clock/stm32fx-clock.h>
+#include <dt-bindings/mfd/stm32f7-rcc.h>
 
 / {
        clocks {
@@ -70,6 +73,13 @@
                        status = "disabled";
                };
 
+               fmc: fmc@A0000000 {
+                       compatible = "st,stm32-fmc";
+                       reg = <0xA0000000 0x1000>;
+                       clocks = <&rcc 0 STM32F7_AHB3_CLOCK(FMC)>;
+                       u-boot,dm-pre-reloc;
+               };
+
                qspi: quadspi@A0001000 {
                        compatible = "st,stm32-qspi";
                        #address-cells = <1>;
@@ -78,13 +88,14 @@
                        reg-names = "QuadSPI", "QuadSPI-memory";
                        interrupts = <92>;
                        spi-max-frequency = <108000000>;
+                       clocks = <&rcc 0 STM32F7_AHB3_CLOCK(QSPI)>;
                        status = "disabled";
                };
                usart1: serial@40011000 {
-                       compatible = "st,stm32-usart", "st,stm32-uart";
+                       compatible = "st,stm32f7-usart", "st,stm32f7-uart";
                        reg = <0x40011000 0x400>;
                        interrupts = <37>;
-                       clocks = <&rcc 0 164>;
+                       clocks = <&rcc 0 STM32F7_APB2_CLOCK(USART1)>;
                        status = "disabled";
                        u-boot,dm-pre-reloc;
                };
@@ -97,7 +108,126 @@
                        u-boot,dm-pre-reloc;
                };
 
+               pinctrl: pin-controller {
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       compatible = "st,stm32f746-pinctrl";
+                       ranges = <0 0x40020000 0x3000>;
+                       u-boot,dm-pre-reloc;
+                       pins-are-numbered;
+
+                       gpioa: gpio@40020000 {
+                               gpio-controller;
+                               #gpio-cells = <2>;
+                               compatible = "st,stm32-gpio";
+                               reg = <0x0 0x400>;
+                               clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOA)>;
+                               st,bank-name = "GPIOA";
+                               u-boot,dm-pre-reloc;
+                       };
+
+                       gpiob: gpio@40020400 {
+                               gpio-controller;
+                               #gpio-cells = <2>;
+                               compatible = "st,stm32-gpio";
+                               reg = <0x400 0x400>;
+                               clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOB)>;
+                               st,bank-name = "GPIOB";
+                               u-boot,dm-pre-reloc;
+                       };
+
+
+                       gpioc: gpio@40020800 {
+                               gpio-controller;
+                               #gpio-cells = <2>;
+                               compatible = "st,stm32-gpio";
+                               reg = <0x800 0x400>;
+                               clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOC)>;
+                               st,bank-name = "GPIOC";
+                               u-boot,dm-pre-reloc;
+                       };
 
+                       gpiod: gpio@40020c00 {
+                               gpio-controller;
+                               #gpio-cells = <2>;
+                               compatible = "st,stm32-gpio";
+                               reg = <0xc00 0x400>;
+                               clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOD)>;
+                               st,bank-name = "GPIOD";
+                               u-boot,dm-pre-reloc;
+                       };
+
+                       gpioe: gpio@40021000 {
+                               gpio-controller;
+                               #gpio-cells = <2>;
+                               compatible = "st,stm32-gpio";
+                               reg = <0x1000 0x400>;
+                               clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOE)>;
+                               st,bank-name = "GPIOE";
+                               u-boot,dm-pre-reloc;
+                       };
+
+                       gpiof: gpio@40021400 {
+                               gpio-controller;
+                               #gpio-cells = <2>;
+                               compatible = "st,stm32-gpio";
+                               reg = <0x1400 0x400>;
+                               clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOF)>;
+                               st,bank-name = "GPIOF";
+                               u-boot,dm-pre-reloc;
+                       };
+
+                       gpiog: gpio@40021800 {
+                               gpio-controller;
+                               #gpio-cells = <2>;
+                               compatible = "st,stm32-gpio";
+                               reg = <0x1800 0x400>;
+                               clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOG)>;
+                               st,bank-name = "GPIOG";
+                               u-boot,dm-pre-reloc;
+                       };
+
+                       gpioh: gpio@40021c00 {
+                               gpio-controller;
+                               #gpio-cells = <2>;
+                               compatible = "st,stm32-gpio";
+                               reg = <0x1c00 0x400>;
+                               clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOH)>;
+                               st,bank-name = "GPIOH";
+                               u-boot,dm-pre-reloc;
+                       };
+
+                       gpioi: gpio@40022000 {
+                               gpio-controller;
+                               #gpio-cells = <2>;
+                               compatible = "st,stm32-gpio";
+                               reg = <0x2000 0x400>;
+                               clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOI)>;
+                               st,bank-name = "GPIOI";
+                               u-boot,dm-pre-reloc;
+                       };
+
+                       gpioj: gpio@40022400 {
+                               gpio-controller;
+                               #gpio-cells = <2>;
+                               compatible = "st,stm32-gpio";
+                               reg = <0x2400 0x400>;
+                               clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOJ)>;
+                               st,bank-name = "GPIOJ";
+                               u-boot,dm-pre-reloc;
+                       };
+
+                       gpiok: gpio@40022800 {
+                               gpio-controller;
+                               #gpio-cells = <2>;
+                               compatible = "st,stm32-gpio";
+                               reg = <0x2800 0x400>;
+                               clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOK)>;
+                               st,bank-name = "GPIOK";
+                               u-boot,dm-pre-reloc;
+                       };
+
+               };
        };
 };