ARM: at91: dt: add dts file for sama5d3 Xplained

[u-boot] / arch / arm / dts / stm32f746.dtsi

diff --git a/arch/arm/dts/stm32f746.dtsi b/arch/arm/dts/stm32f746.dtsi
index f59eca8e03b6da7b4c3dca68fede3fd1bb1bf4c0..b2b0b5f09928ca53cfb4684b97bdaba2a162f7c8 100644 (file)
--- a/arch/arm/dts/stm32f746.dtsi
+++ b/arch/arm/dts/stm32f746.dtsi
@@ -104,6 +104,44 @@
                        ranges = <0 0x40020000 0x3000>;
                        u-boot,dm-pre-reloc;
                        pins-are-numbered;
+
+                       usart1_pins_a: usart1@0 {
+                               pins1 {
+                                       pinmux = <STM32F746_PA9_FUNC_USART1_TX>;
+                                       bias-disable;
+                                       drive-push-pull;
+                                       slew-rate = <2>;
+                               };
+                               pins2 {
+                                       pinmux = <STM32F746_PB7_FUNC_USART1_RX>;
+                                       bias-disable;
+                               };
+                       };
+                       ethernet_mii: mii@0 {
+                               pins {
+                                       pinmux = <STM32F746_PG13_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0>,
+                                                <STM32F746_PG14_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1>,
+                                                <STM32F746_PG11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN>,
+                                                <STM32F746_PA2_FUNC_ETH_MDIO>,
+                                                <STM32F746_PC1_FUNC_ETH_MDC>,
+                                                <STM32F746_PA1_FUNC_ETH_MII_RX_CLK_ETH_RMII_REF_CLK>,
+                                                <STM32F746_PA7_FUNC_ETH_MII_RX_DV_ETH_RMII_CRS_DV>,
+                                                <STM32F746_PC4_FUNC_ETH_MII_RXD0_ETH_RMII_RXD0>,
+                                                <STM32F746_PC5_FUNC_ETH_MII_RXD1_ETH_RMII_RXD1>;
+                                       slew-rate = <2>;
+                               };
+                       };
+                       qspi_pins: qspi@0{
+                               pins {
+                                       pinmux = <STM32F746_PB2_FUNC_QUADSPI_CLK>,
+                                                <STM32F746_PB6_FUNC_QUADSPI_BK1_NCS>,
+                                                <STM32F746_PD11_FUNC_QUADSPI_BK1_IO0>,
+                                                <STM32F746_PD12_FUNC_QUADSPI_BK1_IO1>,
+                                                <STM32F746_PD13_FUNC_QUADSPI_BK1_IO3>,
+                                                <STM32F746_PE2_FUNC_QUADSPI_BK1_IO2>;
+                                       slew-rate = <2>;
+                               };
+                       };
                };
        };
 };