arm: freescale: Rename initdram() to fsl_initdram()

[u-boot] / arch / arm / dts / stm32f746.dtsi

diff --git a/arch/arm/dts/stm32f746.dtsi b/arch/arm/dts/stm32f746.dtsi
index 3902e7625f731f8a412a957d8846895651c016f7..b2b0b5f09928ca53cfb4684b97bdaba2a162f7c8 100644 (file)
--- a/arch/arm/dts/stm32f746.dtsi
+++ b/arch/arm/dts/stm32f746.dtsi
@@ -48,7 +48,16 @@
 #include <dt-bindings/pinctrl/stm32f746-pinfunc.h>
 
 / {
+       clocks {
+               clk_hse: clk-hse {
+                       #clock-cells = <0>;
+                       compatible = "fixed-clock";
+                       clock-frequency = <0>;
+               };
+};
+
        soc {
+               u-boot,dm-pre-reloc;
                mac: ethernet@40028000 {
                        compatible = "st,stm32-dwmac";
                        reg = <0x40028000 0x8000>;
@@ -71,6 +80,69 @@
                        spi-max-frequency = <108000000>;
                        status = "disabled";
                };
+               usart1: serial@40011000 {
+                       compatible = "st,stm32-usart", "st,stm32-uart";
+                       reg = <0x40011000 0x400>;
+                       interrupts = <37>;
+                       clocks = <&rcc 0 164>;
+                       status = "disabled";
+                       u-boot,dm-pre-reloc;
+               };
+               rcc: rcc@40023810 {
+                       #reset-cells = <1>;
+                       #clock-cells = <2>;
+                       compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
+                       reg = <0x40023800 0x400>;
+                       clocks = <&clk_hse>;
+                       u-boot,dm-pre-reloc;
+               };
+
+               pinctrl: pin-controller {
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       compatible = "st,stm32f746-pinctrl";
+                       ranges = <0 0x40020000 0x3000>;
+                       u-boot,dm-pre-reloc;
+                       pins-are-numbered;
+
+                       usart1_pins_a: usart1@0 {
+                               pins1 {
+                                       pinmux = <STM32F746_PA9_FUNC_USART1_TX>;
+                                       bias-disable;
+                                       drive-push-pull;
+                                       slew-rate = <2>;
+                               };
+                               pins2 {
+                                       pinmux = <STM32F746_PB7_FUNC_USART1_RX>;
+                                       bias-disable;
+                               };
+                       };
+                       ethernet_mii: mii@0 {
+                               pins {
+                                       pinmux = <STM32F746_PG13_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0>,
+                                                <STM32F746_PG14_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1>,
+                                                <STM32F746_PG11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN>,
+                                                <STM32F746_PA2_FUNC_ETH_MDIO>,
+                                                <STM32F746_PC1_FUNC_ETH_MDC>,
+                                                <STM32F746_PA1_FUNC_ETH_MII_RX_CLK_ETH_RMII_REF_CLK>,
+                                                <STM32F746_PA7_FUNC_ETH_MII_RX_DV_ETH_RMII_CRS_DV>,
+                                                <STM32F746_PC4_FUNC_ETH_MII_RXD0_ETH_RMII_RXD0>,
+                                                <STM32F746_PC5_FUNC_ETH_MII_RXD1_ETH_RMII_RXD1>;
+                                       slew-rate = <2>;
+                               };
+                       };
+                       qspi_pins: qspi@0{
+                               pins {
+                                       pinmux = <STM32F746_PB2_FUNC_QUADSPI_CLK>,
+                                                <STM32F746_PB6_FUNC_QUADSPI_BK1_NCS>,
+                                                <STM32F746_PD11_FUNC_QUADSPI_BK1_IO0>,
+                                                <STM32F746_PD12_FUNC_QUADSPI_BK1_IO1>,
+                                                <STM32F746_PD13_FUNC_QUADSPI_BK1_IO3>,
+                                                <STM32F746_PE2_FUNC_QUADSPI_BK1_IO2>;
+                                       slew-rate = <2>;
+                               };
+                       };
+               };
        };
 };