armv7: add reset timeout to identify_nand_chip

[u-boot] / arch / arm / dts / sun5i-a13.dtsi

diff --git a/arch/arm/dts/sun5i-a13.dtsi b/arch/arm/dts/sun5i-a13.dtsi
index 976d4faa2179ace0c60d6adc269deb226c314e15..d910d3a6c41c573c83e6c20898cabf072a79ae9b 100644 (file)
--- a/arch/arm/dts/sun5i-a13.dtsi
+++ b/arch/arm/dts/sun5i-a13.dtsi
@@ -104,6 +104,16 @@
                        compatible = "allwinner,sun5i-a13-ahb-gates-clk";
                        reg = <0x01c20060 0x8>;
                        clocks = <&ahb>;
+                       clock-indices = <0>, <1>,
+                                       <2>, <5>, <6>,
+                                       <7>, <8>, <9>,
+                                       <10>, <13>,
+                                       <14>, <20>,
+                                       <21>, <22>,
+                                       <28>, <32>, <36>,
+                                       <40>, <44>,
+                                       <46>, <51>,
+                                       <52>;
                        clock-output-names = "ahb_usbotg", "ahb_ehci",
                                             "ahb_ohci", "ahb_ss", "ahb_dma",
                                             "ahb_bist", "ahb_mmc0", "ahb_mmc1",
@@ -121,6 +131,8 @@
                        compatible = "allwinner,sun5i-a13-apb0-gates-clk";
                        reg = <0x01c20068 0x4>;
                        clocks = <&apb0>;
+                       clock-indices = <0>, <5>,
+                                       <6>;
                        clock-output-names = "apb0_codec", "apb0_pio",
                                             "apb0_ir";
                };
@@ -130,8 +142,22 @@
                        compatible = "allwinner,sun5i-a13-apb1-gates-clk";
                        reg = <0x01c2006c 0x4>;
                        clocks = <&apb1>;
+                       clock-indices = <0>, <1>,
+                                       <2>, <17>,
+                                       <19>;
                        clock-output-names = "apb1_i2c0", "apb1_i2c1",
-                               "apb1_i2c2", "apb1_uart1", "apb1_uart3";
+                                            "apb1_i2c2", "apb1_uart1",
+                                            "apb1_uart3";
+               };
+       };
+
+       soc@01c00000 {
+               pwm: pwm@01c20e00 {
+                       compatible = "allwinner,sun5i-a13-pwm";
+                       reg = <0x01c20e00 0xc>;
+                       clocks = <&osc24M>;
+                       #pwm-cells = <3>;
+                       status = "disabled";
                };
        };
 };