Merge branch 'master' of http://git.denx.de/u-boot-sunxi

[u-boot] / arch / arm / dts / sun7i-a20.dtsi

diff --git a/arch/arm/dts/sun7i-a20.dtsi b/arch/arm/dts/sun7i-a20.dtsi
index 71ab6b85f240a2478a698df9a5590096b4c5bbc5..0940a788f824396d318214d8ab3d148227cc8fc5 100644 (file)
--- a/arch/arm/dts/sun7i-a20.dtsi
+++ b/arch/arm/dts/sun7i-a20.dtsi
@@ -47,6 +47,7 @@
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/thermal/thermal.h>
 
+#include <dt-bindings/clock/sun4i-a10-pll2.h>
 #include <dt-bindings/dma/sun4i-a10.h>
 #include <dt-bindings/pinctrl/sun4i-a10.h>
 
@@ -67,7 +68,7 @@
                                     "simple-framebuffer";
                        allwinner,pipeline = "de_be0-lcd0-hdmi";
                        clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,
-                                <&ahb_gates 44>;
+                                <&ahb_gates 44>, <&dram_gates 26>;
                        status = "disabled";
                };
 
@@ -75,7 +76,8 @@
                        compatible = "allwinner,simple-framebuffer",
                                     "simple-framebuffer";
                        allwinner,pipeline = "de_be0-lcd0";
-                       clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>;
+                       clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>,
+                                <&dram_gates 26>;
                        status = "disabled";
                };
 
@@ -84,7 +86,7 @@
                                     "simple-framebuffer";
                        allwinner,pipeline = "de_be0-lcd0-tve0";
                        clocks = <&pll5 1>, <&ahb_gates 34>, <&ahb_gates 36>,
-                                <&ahb_gates 44>;
+                                <&ahb_gates 44>, <&dram_gates 26>;
                        status = "disabled";
                };
        };
@@ -107,7 +109,7 @@
                                720000  1200000
                                528000  1100000
                                312000  1000000
-                               144000  900000
+                               144000  1000000
                                >;
                        #cooling-cells = <2>;
                        cooling-min-level = <0>;
@@ -199,6 +201,15 @@
                        clock-output-names = "pll1";
                };
 
+               pll2: clk@01c20008 {
+                       #clock-cells = <1>;
+                       compatible = "allwinner,sun4i-a10-pll2-clk";
+                       reg = <0x01c20008 0x8>;
+                       clocks = <&osc24M>;
+                       clock-output-names = "pll2-1x", "pll2-2x",
+                                            "pll2-4x", "pll2-8x";
+               };
+
                pll4: clk@01c20018 {
                        #clock-cells = <0>;
                        compatible = "allwinner,sun7i-a20-pll4-clk";
@@ -267,6 +278,19 @@
                        compatible = "allwinner,sun7i-a20-ahb-gates-clk";
                        reg = <0x01c20060 0x8>;
                        clocks = <&ahb>;
+                       clock-indices = <0>, <1>,
+                                       <2>, <3>, <4>,
+                                       <5>, <6>, <7>, <8>,
+                                       <9>, <10>, <11>, <12>,
+                                       <13>, <14>, <16>,
+                                       <17>, <18>, <20>, <21>,
+                                       <22>, <23>, <25>,
+                                       <28>, <32>, <33>, <34>,
+                                       <35>, <36>, <37>, <40>,
+                                       <41>, <42>, <43>,
+                                       <44>, <45>, <46>,
+                                       <47>, <49>, <50>,
+                                       <52>;
                        clock-output-names = "ahb_usb0", "ahb_ehci0",
                                "ahb_ohci0", "ahb_ehci1", "ahb_ohci1",
                                "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
@@ -295,6 +319,10 @@
                        compatible = "allwinner,sun7i-a20-apb0-gates-clk";
                        reg = <0x01c20068 0x4>;
                        clocks = <&apb0>;
+                       clock-indices = <0>, <1>,
+                                       <2>, <3>, <4>,
+                                       <5>, <6>, <7>,
+                                       <8>, <10>;
                        clock-output-names = "apb0_codec", "apb0_spdif",
                                "apb0_ac97", "apb0_iis0", "apb0_iis1",
                                "apb0_pio", "apb0_ir0", "apb0_ir1",
@@ -314,6 +342,12 @@
                        compatible = "allwinner,sun7i-a20-apb1-gates-clk";
                        reg = <0x01c2006c 0x4>;
                        clocks = <&apb1>;
+                       clock-indices = <0>, <1>,
+                                       <2>, <3>, <4>,
+                                       <5>, <6>, <7>,
+                                       <15>, <16>, <17>,
+                                       <18>, <19>, <20>,
+                                       <21>, <22>, <23>;
                        clock-output-names = "apb1_i2c0", "apb1_i2c1",
                                "apb1_i2c2", "apb1_i2c3", "apb1_can",
                                "apb1_scr", "apb1_ps20", "apb1_ps21",
@@ -442,6 +476,14 @@
                        clock-output-names = "ir1";
                };
 
+               keypad_clk: clk@01c200c4 {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-a10-mod0-clk";
+                       reg = <0x01c200c4 0x4>;
+                       clocks = <&osc24M>;
+                       clock-output-names = "keypad";
+               };
+
                usb_clk: clk@01c200cc {
                        #clock-cells = <1>;
                        #reset-cells = <1>;
@@ -460,6 +502,48 @@
                        clock-output-names = "spi3";
                };
 
+               dram_gates: clk@01c20100 {
+                       #clock-cells = <1>;
+                       compatible = "allwinner,sun4i-a10-dram-gates-clk";
+                       reg = <0x01c20100 0x4>;
+                       clocks = <&pll5 0>;
+                       clock-indices = <0>,
+                                       <1>, <2>,
+                                       <3>,
+                                       <4>,
+                                       <5>, <6>,
+                                       <15>,
+                                       <24>, <25>,
+                                       <26>, <27>,
+                                       <28>, <29>;
+                       clock-output-names = "dram_ve",
+                                            "dram_csi0", "dram_csi1",
+                                            "dram_ts",
+                                            "dram_tvd",
+                                            "dram_tve0", "dram_tve1",
+                                            "dram_output",
+                                            "dram_de_fe1", "dram_de_fe0",
+                                            "dram_de_be0", "dram_de_be1",
+                                            "dram_de_mp", "dram_ace";
+               };
+
+               ve_clk: clk@01c2013c {
+                       #clock-cells = <0>;
+                       #reset-cells = <0>;
+                       compatible = "allwinner,sun4i-a10-ve-clk";
+                       reg = <0x01c2013c 0x4>;
+                       clocks = <&pll4>;
+                       clock-output-names = "ve";
+               };
+
+               codec_clk: clk@01c20140 {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-a10-codec-clk";
+                       reg = <0x01c20140 0x4>;
+                       clocks = <&pll2 SUN4I_A10_PLL2_1X>;
+                       clock-output-names = "codec";
+               };
+
                mbus_clk: clk@01c2015c {
                        #clock-cells = <0>;
                        compatible = "allwinner,sun5i-a13-mbus-clk";
@@ -744,6 +828,14 @@
                        status = "disabled";
                };
 
+               crypto: crypto-engine@01c15000 {
+                       compatible = "allwinner,sun4i-a10-crypto";
+                       reg = <0x01c15000 0x1000>;
+                       interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&ahb_gates 5>, <&ss_clk>;
+                       clock-names = "ahb", "mod";
+               };
+
                spi2: spi@01c17000 {
                        compatible = "allwinner,sun4i-a10-spi";
                        reg = <0x01c17000 0x1000>;
@@ -1159,6 +1251,19 @@
                        status = "disabled";
                };
 
+               codec: codec@01c22c00 {
+                       #sound-dai-cells = <0>;
+                       compatible = "allwinner,sun7i-a20-codec";
+                       reg = <0x01c22c00 0x40>;
+                       interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&apb0_gates 0>, <&codec_clk>;
+                       clock-names = "apb", "codec";
+                       dmas = <&dma SUN4I_DMA_NORMAL 19>,
+                              <&dma SUN4I_DMA_NORMAL 19>;
+                       dma-names = "rx", "tx";
+                       status = "disabled";
+               };
+
                sid: eeprom@01c23800 {
                        compatible = "allwinner,sun7i-a20-sid";
                        reg = <0x01c23800 0x200>;