]> git.sur5r.net Git - u-boot/blobdiff - arch/arm/dts/tegra20-whistler.dts
aspeed: Device Tree configuration for Reset Driver
[u-boot] / arch / arm / dts / tegra20-whistler.dts
index 4fd2496dbc57f07e5c42771814c0ac5df04a34aa..447874674d72068b66c7d22217500fbd7b295443 100644 (file)
@@ -13,8 +13,8 @@
        aliases {
                i2c0 = "/i2c@7000d000";
                usb0 = "/usb@c5008000";
-               sdhci0 = "/sdhci@c8000600";
-               sdhci1 = "/sdhci@c8000400";
+               mmc0 = "/sdhci@c8000600";
+               mmc1 = "/sdhci@c8000400";
        };
 
        memory {
                clock-frequency = < 216000000 >;
        };
 
-       i2c@7000c000 {
-               status = "disabled";
-       };
-
-       i2c@7000c400 {
-               status = "disabled";
-       };
-
-       i2c@7000c500 {
-               status = "disabled";
-       };
-
        i2c@7000d000 {
+               status = "okay";
                clock-frequency = <100000>;
 
                pmic@3c {
                };
        };
 
-       usb@c5000000 {
-               status = "disabled";
-       };
-
-       usb@c5004000 {
-               status = "disabled";
+       usb@c5008000 {
+               status = "okay";
        };
 
        sdhci@c8000400 {
                status = "okay";
-               wp-gpios = <&gpio 173 0>; /* gpio PV5 */
+               wp-gpios = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_HIGH>;
                bus-width = <8>;
        };
 
        sdhci@c8000600 {
                status = "okay";
                bus-width = <8>;
+               non-removable;
        };
+
+       clocks {
+               compatible = "simple-bus";
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               clk32k_in: clock@0 {
+                       compatible = "fixed-clock";
+                       reg=<0>;
+                       #clock-cells = <0>;
+                       clock-frequency = <32768>;
+               };
+       };
+
 };