ARM: at91: dt: add dts file for sama5d3 Xplained

[u-boot] / arch / arm / dts / tegra30-apalis.dts

diff --git a/arch/arm/dts/tegra30-apalis.dts b/arch/arm/dts/tegra30-apalis.dts
index 3e0545c8befb18dc4f282ad17a0d2736652a1fe8..9e4ab8c26f13d1a8e42226f8e737d15db0363602 100644 (file)
--- a/arch/arm/dts/tegra30-apalis.dts
+++ b/arch/arm/dts/tegra30-apalis.dts
@@ -15,9 +15,9 @@
                i2c1 = "/i2c@7000c000";
                i2c2 = "/i2c@7000c500";
                i2c3 = "/i2c@7000c700";
-               sdhci0 = "/sdhci@78000600";
-               sdhci1 = "/sdhci@78000400";
-               sdhci2 = "/sdhci@78000000";
+               mmc0 = "/sdhci@78000600";
+               mmc1 = "/sdhci@78000400";
+               mmc2 = "/sdhci@78000000";
                spi0 = "/spi@7000d400";
                spi1 = "/spi@7000dc00";
                spi2 = "/spi@7000de00";
@@ -44,10 +44,12 @@
                hvdd-pex-supply = <&sys_3v3_reg>;
 
                pci@1,0 {
+                       /* TS_DIFF1/2/3/4 left disabled */
                        nvidia,num-lanes = <4>;
                };
 
                pci@2,0 {
+                       /* PCIE1_RX/TX left disabled */
                        nvidia,num-lanes = <1>;
                };
 
@@ -277,7 +279,6 @@
                status = "okay";
                /* USBH_EN */
                nvidia,vbus-gpio = <&gpio TEGRA_GPIO(DD, 1) GPIO_ACTIVE_HIGH>;
-               phy_type = "utmi";
        };
 
        /* EHCI instance 2: USB3_DP/N -> USBH3_DP/N */
@@ -287,6 +288,26 @@
                nvidia,vbus-gpio = <&gpio TEGRA_GPIO(DD, 1) GPIO_ACTIVE_HIGH>;
        };
 
+       clocks {
+               compatible = "simple-bus";
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               clk32k_in: clk@0 {
+                       compatible = "fixed-clock";
+                       reg=<0>;
+                       #clock-cells = <0>;
+                       clock-frequency = <32768>;
+               };
+               clk16m: clk@1 {
+                       compatible = "fixed-clock";
+                       reg=<1>;
+                       #clock-cells = <0>;
+                       clock-frequency = <16000000>;
+                       clock-output-names = "clk16m";
+               };
+       };
+
        regulators {
                compatible = "simple-bus";
                #address-cells = <1>;