arm64: allwinner: a64: bananapi-m64: Sync usb_otg node from Linux

[u-boot] / arch / arm / dts / uniphier-ld20-ref.dts

diff --git a/arch/arm/dts/uniphier-ld20-ref.dts b/arch/arm/dts/uniphier-ld20-ref.dts
index 044e0007492c0b6206b2768d809103f6da381604..440c2e6a638b998c163b3f8aea91f94e115f516b 100644 (file)
--- a/arch/arm/dts/uniphier-ld20-ref.dts
+++ b/arch/arm/dts/uniphier-ld20-ref.dts
@@ -1,21 +1,23 @@
-/*
- * Device Tree Source for UniPhier LD20 Reference Board
- *
- * Copyright (C) 2015-2016 Socionext Inc.
- *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier:    GPL-2.0+        X11
- */
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+//
+// Device Tree Source for UniPhier LD20 Reference Board
+//
+// Copyright (C) 2015-2016 Socionext Inc.
+//   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
 
 /dts-v1/;
-/include/ "uniphier-ld20.dtsi"
-/include/ "uniphier-ref-daughter.dtsi"
-/include/ "uniphier-support-card.dtsi"
+#include "uniphier-ld20.dtsi"
+#include "uniphier-ref-daughter.dtsi"
+#include "uniphier-support-card.dtsi"
 
 / {
        model = "UniPhier LD20 Reference Board";
        compatible = "socionext,uniphier-ld20-ref", "socionext,uniphier-ld20";
 
+       chosen {
+               stdout-path = "serial0:115200n8";
+       };
+
        aliases {
                serial0 = &serial0;
                serial1 = &serial1;
@@ -29,37 +31,47 @@
                i2c5 = &i2c5;
        };
 
-       memory {
+       memory@80000000 {
                device_type = "memory";
                reg = <0 0x80000000 0 0xc0000000>;
        };
-
-       chosen {
-               stdout-path = "serial0:115200n8";
-       };
 };
 
 &ethsc {
-       interrupts = <0 48 4>;
+       interrupts = <0 8>;
 };
 
 &serial0 {
        status = "okay";
 };
 
+&gpio {
+       xirq0 {
+               gpio-hog;
+               gpios = <UNIPHIER_GPIO_IRQ(0) 0>;
+               input;
+       };
+};
+
 &i2c0 {
        status = "okay";
 };
 
-/* for U-Boot only */
-&serial0 {
-       u-boot,dm-pre-reloc;
+&eth {
+       status = "okay";
+       phy-handle = <&ethphy>;
 };
 
-&pinctrl_uart0 {
-       u-boot,dm-pre-reloc;
+&mdio {
+       ethphy: ethphy@0 {
+               reg = <0>;
+       };
 };
 
-&pinctrl_system_bus {
-       u-boot,dm-pre-reloc;
+&pinctrl_ether_rgmii {
+       tx {
+               pins = "RGMII_TXCLK", "RGMII_TXD0", "RGMII_TXD1",
+                      "RGMII_TXD2", "RGMII_TXD3", "RGMII_TXCTL";
+               drive-strength = <9>;
+       };
 };