]> git.sur5r.net Git - u-boot/blobdiff - arch/arm/dts/uniphier-ph1-ld11.dtsi
arm64: mvebu: armada-7040-db.dts: Add I2C and SPI aliases
[u-boot] / arch / arm / dts / uniphier-ph1-ld11.dtsi
index ffe04f5cb69b15bb6012bc1891f12b627ab61344..0bdbbddd9dde20aef63026172eb275d118ac6b27 100644 (file)
                        clock-frequency = <25000000>;
                };
 
-               uart_clk: uart_clk {
-                       #clock-cells = <0>;
-                       compatible = "fixed-clock";
-                       clock-frequency = <58820000>;
-               };
-
                i2c_clk: i2c_clk {
                        #clock-cells = <0>;
                        compatible = "fixed-clock";
 
        timer {
                compatible = "arm,armv8-timer";
-               interrupts = <1 13 0xf01>,
-                            <1 14 0xf01>,
-                            <1 11 0xf01>,
-                            <1 10 0xf01>;
+               interrupts = <1 13 4>,
+                            <1 14 4>,
+                            <1 11 4>,
+                            <1 10 4>;
        };
 
        soc {
@@ -89,7 +83,7 @@
                        interrupts = <0 33 4>;
                        pinctrl-names = "default";
                        pinctrl-0 = <&pinctrl_uart0>;
-                       clocks = <&uart_clk>;
+                       clocks = <&peri_clk 0>;
                        clock-frequency = <58820000>;
                };
 
                        interrupts = <0 35 4>;
                        pinctrl-names = "default";
                        pinctrl-0 = <&pinctrl_uart1>;
-                       clocks = <&uart_clk>;
+                       clocks = <&peri_clk 1>;
                        clock-frequency = <58820000>;
                };
 
                        interrupts = <0 37 4>;
                        pinctrl-names = "default";
                        pinctrl-0 = <&pinctrl_uart2>;
-                       clocks = <&uart_clk>;
+                       clocks = <&peri_clk 2>;
                        clock-frequency = <58820000>;
                };
 
                        interrupts = <0 177 4>;
                        pinctrl-names = "default";
                        pinctrl-0 = <&pinctrl_uart3>;
-                       clocks = <&uart_clk>;
+                       clocks = <&peri_clk 3>;
                        clock-frequency = <58820000>;
                };
 
                        reg = <0x59801000 0x400>;
                };
 
+               perictrl@59820000 {
+                       compatible = "socionext,uniphier-perictrl",
+                                    "simple-mfd", "syscon";
+                       reg = <0x59820000 0x200>;
+
+                       peri_clk: clock {
+                               compatible = "socionext,uniphier-ld11-peri-clock";
+                               #clock-cells = <1>;
+                       };
+
+                       peri_rst: reset {
+                               compatible = "socionext,uniphier-ld11-peri-reset";
+                               #reset-cells = <1>;
+                       };
+               };
+
                usb0: usb@5a800100 {
                        compatible = "socionext,uniphier-ehci", "generic-ehci";
                        status = "disabled";
                        interrupts = <0 243 4>;
                        pinctrl-names = "default";
                        pinctrl-0 = <&pinctrl_usb0>;
-                       clocks = <&mio 3>, <&mio 6>;
+                       clocks = <&mio_clk 3>, <&mio_clk 6>;
                };
 
                usb1: usb@5a810100 {
                        interrupts = <0 244 4>;
                        pinctrl-names = "default";
                        pinctrl-0 = <&pinctrl_usb1>;
-                       clocks = <&mio 4>, <&mio 6>;
+                       clocks = <&mio_clk 4>, <&mio_clk 6>;
                };
 
                usb2: usb@5a820100 {
                        interrupts = <0 245 4>;
                        pinctrl-names = "default";
                        pinctrl-0 = <&pinctrl_usb2>;
-                       clocks = <&mio 5>, <&mio 6>;
+                       clocks = <&mio_clk 5>, <&mio_clk 6>;
                };
 
-               mio: mioctrl@5b3e0000 {
-                       compatible = "socionext,ph1-ld11-mioctrl";
+               mioctrl@5b3e0000 {
+                       compatible = "socionext,uniphier-mioctrl",
+                                    "simple-mfd", "syscon";
                        reg = <0x5b3e0000 0x800>;
-                       #clock-cells = <1>;
+
+                       mio_clk: clock {
+                               compatible = "socionext,uniphier-ld11-mio-clock";
+                               #clock-cells = <1>;
+                       };
+
+                       mio_rst: reset {
+                               compatible = "socionext,uniphier-ld11-mio-reset";
+                               #reset-cells = <1>;
+                               resets = <&sys_rst 7>;
+                       };
                };
 
                soc-glue@5f800000 {
-                       compatible = "simple-mfd", "syscon";
+                       compatible = "socionext,uniphier-soc-glue",
+                                    "simple-mfd", "syscon";
                        reg = <0x5f800000 0x2000>;
                        u-boot,dm-pre-reloc;
 
                        #interrupt-cells = <3>;
                        interrupts = <1 9 4>;
                };
+
+               sysctrl@61840000 {
+                       compatible = "socionext,uniphier-ld11-sysctrl",
+                                    "simple-mfd", "syscon";
+                       reg = <0x61840000 0x4000>;
+
+                       sys_clk: clock {
+                               compatible = "socionext,uniphier-ld11-clock";
+                               #clock-cells = <1>;
+                       };
+
+                       sys_rst: reset {
+                               compatible = "socionext,uniphier-ld11-reset";
+                               #reset-cells = <1>;
+                       };
+               };
        };
 };