Merge branch 'master' of git://www.denx.de/git/u-boot-imx

[u-boot] / arch / arm / dts / uniphier-ph1-ld20.dtsi

diff --git a/arch/arm/dts/uniphier-ph1-ld20.dtsi b/arch/arm/dts/uniphier-ph1-ld20.dtsi
index f9cc3c4bdbcbf1119a243675ff0272dea6812b96..7497539467b00865f2a846c9326655b03fe725ff 100644 (file)
--- a/arch/arm/dts/uniphier-ph1-ld20.dtsi
+++ b/arch/arm/dts/uniphier-ph1-ld20.dtsi
@@ -6,6 +6,8 @@
  * SPDX-License-Identifier:    GPL-2.0+        X11
  */
 
+/memreserve/ 0x80000000 0x00000008;    /* cpu-release-addr */
+
 / {
        compatible = "socionext,ph1-ld20";
        #address-cells = <2>;
@@ -41,7 +43,7 @@
                        compatible = "arm,cortex-a72", "arm,armv8";
                        reg = <0 0x000>;
                        enable-method = "spin-table";
-                       cpu-release-addr = <0 0x80000100>;
+                       cpu-release-addr = <0 0x80000000>;
                };
 
                cpu1: cpu@1 {
@@ -49,7 +51,7 @@
                        compatible = "arm,cortex-a72", "arm,armv8";
                        reg = <0 0x001>;
                        enable-method = "spin-table";
-                       cpu-release-addr = <0 0x80000100>;
+                       cpu-release-addr = <0 0x80000000>;
                };
 
                cpu2: cpu@100 {
@@ -57,7 +59,7 @@
                        compatible = "arm,cortex-a53", "arm,armv8";
                        reg = <0 0x100>;
                        enable-method = "spin-table";
-                       cpu-release-addr = <0 0x80000100>;
+                       cpu-release-addr = <0 0x80000000>;
                };
 
                cpu3: cpu@101 {
@@ -65,11 +67,17 @@
                        compatible = "arm,cortex-a53", "arm,armv8";
                        reg = <0 0x101>;
                        enable-method = "spin-table";
-                       cpu-release-addr = <0 0x80000100>;
+                       cpu-release-addr = <0 0x80000000>;
                };
        };
 
        clocks {
+               refclk: ref {
+                       compatible = "fixed-clock";
+                       #clock-cells = <0>;
+                       clock-frequency = <25000000>;
+               };
+
                uart_clk: uart_clk {
                        #clock-cells = <0>;
                        compatible = "fixed-clock";
@@ -96,6 +104,7 @@
                #address-cells = <1>;
                #size-cells = <1>;
                ranges = <0 0 0 0xffffffff>;
+               u-boot,dm-pre-reloc;
 
                serial0: serial@54006800 {
                        compatible = "socionext,uniphier-uart";
@@ -219,6 +228,8 @@
                        reg = <0x58c00000 0x400>;
                        #address-cells = <2>;
                        #size-cells = <1>;
+                       pinctrl-names = "default";
+                       pinctrl-0 = <&pinctrl_system_bus>;
                };
 
                smpctrl@59800000 {
@@ -243,9 +254,20 @@
                        bus-width = <4>;
                };
 
-               pinctrl: pinctrl@5f801000 {
-                       compatible = "socionext,ph1-ld20-pinctrl", "syscon";
-                       reg = <0x5f801000 0xe00>;
+               soc-glue@5f800000 {
+                       compatible = "simple-mfd", "syscon";
+                       reg = <0x5f800000 0x2000>;
+                       u-boot,dm-pre-reloc;
+
+                       pinctrl: pinctrl {
+                               compatible = "socionext,uniphier-ld20-pinctrl";
+                               u-boot,dm-pre-reloc;
+                       };
+               };
+
+               aidet@5fc20000 {
+                       compatible = "simple-mfd", "syscon";
+                       reg = <0x5fc20000 0x200>;
                };
 
                gic: interrupt-controller@5fe00000 {