ARM: tegra: fdt: Add 'non-removable' property to all eMMC nodes

[u-boot] / arch / arm / dts / uniphier-ph1-ld20.dtsi

diff --git a/arch/arm/dts/uniphier-ph1-ld20.dtsi b/arch/arm/dts/uniphier-ph1-ld20.dtsi
index fc1c6bfe5bc037bf3919d5563794efdcaa3ae194..7f97f8816a4ddf51a17508d8b5ca734043fcaeba 100644 (file)
--- a/arch/arm/dts/uniphier-ph1-ld20.dtsi
+++ b/arch/arm/dts/uniphier-ph1-ld20.dtsi
@@ -6,6 +6,8 @@
  * SPDX-License-Identifier:    GPL-2.0+        X11
  */
 
+/memreserve/ 0x80000000 0x00000008;    /* cpu-release-addr */
+
 / {
        compatible = "socionext,ph1-ld20";
        #address-cells = <2>;
@@ -41,7 +43,7 @@
                        compatible = "arm,cortex-a72", "arm,armv8";
                        reg = <0 0x000>;
                        enable-method = "spin-table";
-                       cpu-release-addr = <0 0x80000100>;
+                       cpu-release-addr = <0 0x80000000>;
                };
 
                cpu1: cpu@1 {
@@ -49,7 +51,7 @@
                        compatible = "arm,cortex-a72", "arm,armv8";
                        reg = <0 0x001>;
                        enable-method = "spin-table";
-                       cpu-release-addr = <0 0x80000100>;
+                       cpu-release-addr = <0 0x80000000>;
                };
 
                cpu2: cpu@100 {
@@ -57,7 +59,7 @@
                        compatible = "arm,cortex-a53", "arm,armv8";
                        reg = <0 0x100>;
                        enable-method = "spin-table";
-                       cpu-release-addr = <0 0x80000100>;
+                       cpu-release-addr = <0 0x80000000>;
                };
 
                cpu3: cpu@101 {
@@ -65,15 +67,15 @@
                        compatible = "arm,cortex-a53", "arm,armv8";
                        reg = <0 0x101>;
                        enable-method = "spin-table";
-                       cpu-release-addr = <0 0x80000100>;
+                       cpu-release-addr = <0 0x80000000>;
                };
        };
 
        clocks {
-               uart_clk: uart_clk {
-                       #clock-cells = <0>;
+               refclk: ref {
                        compatible = "fixed-clock";
-                       clock-frequency = <58820000>;
+                       #clock-cells = <0>;
+                       clock-frequency = <25000000>;
                };
 
                i2c_clk: i2c_clk {
@@ -85,10 +87,10 @@
 
        timer {
                compatible = "arm,armv8-timer";
-               interrupts = <1 13 0xf01>,
-                            <1 14 0xf01>,
-                            <1 11 0xf01>,
-                            <1 10 0xf01>;
+               interrupts = <1 13 4>,
+                            <1 14 4>,
+                            <1 11 4>,
+                            <1 10 4>;
        };
 
        soc {
@@ -96,6 +98,7 @@
                #address-cells = <1>;
                #size-cells = <1>;
                ranges = <0 0 0 0xffffffff>;
+               u-boot,dm-pre-reloc;
 
                serial0: serial@54006800 {
                        compatible = "socionext,uniphier-uart";
@@ -104,7 +107,7 @@
                        interrupts = <0 33 4>;
                        pinctrl-names = "default";
                        pinctrl-0 = <&pinctrl_uart0>;
-                       clocks = <&uart_clk>;
+                       clocks = <&peri_clk 0>;
                        clock-frequency = <58820000>;
                };
 
@@ -115,7 +118,7 @@
                        interrupts = <0 35 4>;
                        pinctrl-names = "default";
                        pinctrl-0 = <&pinctrl_uart1>;
-                       clocks = <&uart_clk>;
+                       clocks = <&peri_clk 1>;
                        clock-frequency = <58820000>;
                };
 
@@ -126,7 +129,7 @@
                        interrupts = <0 37 4>;
                        pinctrl-names = "default";
                        pinctrl-0 = <&pinctrl_uart2>;
-                       clocks = <&uart_clk>;
+                       clocks = <&peri_clk 2>;
                        clock-frequency = <58820000>;
                };
 
@@ -137,7 +140,7 @@
                        interrupts = <0 177 4>;
                        pinctrl-names = "default";
                        pinctrl-0 = <&pinctrl_uart3>;
-                       clocks = <&uart_clk>;
+                       clocks = <&peri_clk 3>;
                        clock-frequency = <58820000>;
                };
 
@@ -219,6 +222,8 @@
                        reg = <0x58c00000 0x400>;
                        #address-cells = <2>;
                        #size-cells = <1>;
+                       pinctrl-names = "default";
+                       pinctrl-0 = <&pinctrl_system_bus>;
                };
 
                smpctrl@59800000 {
@@ -226,9 +231,64 @@
                        reg = <0x59801000 0x400>;
                };
 
-               pinctrl: pinctrl@5f801000 {
-                       compatible = "socionext,ph1-ld20-pinctrl", "syscon";
-                       reg = <0x5f801000 0xe00>;
+               mioctrl@59810000 {
+                       compatible = "socionext,uniphier-mioctrl",
+                                    "simple-mfd", "syscon";
+                       reg = <0x59810000 0x800>;
+
+                       mio_clk: clock {
+                               compatible = "socionext,uniphier-ld20-mio-clock";
+                               #clock-cells = <1>;
+                       };
+
+                       mio_rst: reset {
+                               compatible = "socionext,uniphier-ld20-mio-reset";
+                               #reset-cells = <1>;
+                       };
+               };
+
+               perictrl@59820000 {
+                       compatible = "socionext,uniphier-perictrl",
+                                    "simple-mfd", "syscon";
+                       reg = <0x59820000 0x200>;
+
+                       peri_clk: clock {
+                               compatible = "socionext,uniphier-ld20-peri-clock";
+                               #clock-cells = <1>;
+                       };
+
+                       peri_rst: reset {
+                               compatible = "socionext,uniphier-ld20-peri-reset";
+                               #reset-cells = <1>;
+                       };
+               };
+
+               sd: sdhc@5a400000 {
+                       compatible = "socionext,uniphier-sdhc";
+                       status = "disabled";
+                       reg = <0x5a400000 0x800>;
+                       interrupts = <0 76 4>;
+                       pinctrl-names = "default";
+                       pinctrl-0 = <&pinctrl_sd>;
+                       clocks = <&mio_clk 0>;
+                       bus-width = <4>;
+               };
+
+               soc-glue@5f800000 {
+                       compatible = "socionext,uniphier-soc-glue",
+                                    "simple-mfd", "syscon";
+                       reg = <0x5f800000 0x2000>;
+                       u-boot,dm-pre-reloc;
+
+                       pinctrl: pinctrl {
+                               compatible = "socionext,uniphier-ld20-pinctrl";
+                               u-boot,dm-pre-reloc;
+                       };
+               };
+
+               aidet@5fc20000 {
+                       compatible = "simple-mfd", "syscon";
+                       reg = <0x5fc20000 0x200>;
                };
 
                gic: interrupt-controller@5fe00000 {
@@ -239,6 +299,22 @@
                        #interrupt-cells = <3>;
                        interrupts = <1 9 4>;
                };
+
+               sysctrl@61840000 {
+                       compatible = "socionext,uniphier-sysctrl",
+                                    "simple-mfd", "syscon";
+                       reg = <0x61840000 0x4000>;
+
+                       sys_clk: clock {
+                               compatible = "socionext,uniphier-ld20-clock";
+                               #clock-cells = <1>;
+                       };
+
+                       sys_rst: reset {
+                               compatible = "socionext,uniphier-ld20-reset";
+                               #reset-cells = <1>;
+                       };
+               };
        };
 };