-/*
- * Device Tree Source for UniPhier PXs2 SoC
- *
- * Copyright (C) 2015-2016 Socionext Inc.
- * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+ X11
- */
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+//
+// Device Tree Source for UniPhier PXs2 SoC
+//
+// Copyright (C) 2015-2016 Socionext Inc.
+// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
-/include/ "skeleton.dtsi"
+#include <dt-bindings/gpio/uniphier-gpio.h>
+#include <dt-bindings/thermal/thermal.h>
/ {
compatible = "socionext,uniphier-pxs2";
+ #address-cells = <1>;
+ #size-cells = <1>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
- cpu@0 {
+ cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0>;
enable-method = "psci";
next-level-cache = <&l2>;
operating-points-v2 = <&cpu_opp>;
+ #cooling-cells = <2>;
};
- cpu@1 {
+ cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <1>;
operating-points-v2 = <&cpu_opp>;
};
- cpu@2 {
+ cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <2>;
operating-points-v2 = <&cpu_opp>;
};
- cpu@3 {
+ cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <3>;
};
};
- cpu_opp: opp_table {
+ cpu_opp: opp-table {
compatible = "operating-points-v2";
opp-shared;
- opp@100000000 {
+ opp-100000000 {
opp-hz = /bits/ 64 <100000000>;
clock-latency-ns = <300>;
};
- opp@150000000 {
+ opp-150000000 {
opp-hz = /bits/ 64 <150000000>;
clock-latency-ns = <300>;
};
- opp@200000000 {
+ opp-200000000 {
opp-hz = /bits/ 64 <200000000>;
clock-latency-ns = <300>;
};
- opp@300000000 {
+ opp-300000000 {
opp-hz = /bits/ 64 <300000000>;
clock-latency-ns = <300>;
};
- opp@400000000 {
+ opp-400000000 {
opp-hz = /bits/ 64 <400000000>;
clock-latency-ns = <300>;
};
- opp@600000000 {
+ opp-600000000 {
opp-hz = /bits/ 64 <600000000>;
clock-latency-ns = <300>;
};
- opp@800000000 {
+ opp-800000000 {
opp-hz = /bits/ 64 <800000000>;
clock-latency-ns = <300>;
};
- opp@1200000000 {
+ opp-1200000000 {
opp-hz = /bits/ 64 <1200000000>;
clock-latency-ns = <300>;
};
clock-frequency = <25000000>;
};
- arm_timer_clk: arm_timer_clk {
+ arm_timer_clk: arm-timer {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <50000000>;
};
+ };
- i2c_clk: i2c_clk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <50000000>;
+ thermal-zones {
+ cpu-thermal {
+ polling-delay-passive = <250>; /* 250ms */
+ polling-delay = <1000>; /* 1000ms */
+ thermal-sensors = <&pvtctl>;
+
+ trips {
+ cpu_crit: cpu-crit {
+ temperature = <95000>; /* 95C */
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ cpu_alert: cpu-alert {
+ temperature = <85000>; /* 85C */
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ map {
+ trip = <&cpu_alert>;
+ cooling-device = <&cpu0
+ THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
};
};
#size-cells = <1>;
ranges;
interrupt-parent = <&intc>;
- u-boot,dm-pre-reloc;
l2: l2-cache@500c0000 {
compatible = "socionext,uniphier-system-cache";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0>;
clocks = <&peri_clk 0>;
- clock-frequency = <88900000>;
+ resets = <&peri_rst 0>;
};
serial1: serial@54006900 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
clocks = <&peri_clk 1>;
- clock-frequency = <88900000>;
+ resets = <&peri_rst 1>;
};
serial2: serial@54006a00 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
clocks = <&peri_clk 2>;
- clock-frequency = <88900000>;
+ resets = <&peri_rst 2>;
};
serial3: serial@54006b00 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
clocks = <&peri_clk 3>;
- clock-frequency = <88900000>;
+ resets = <&peri_rst 3>;
};
- port0x: gpio@55000008 {
+ gpio: gpio@55000000 {
compatible = "socionext,uniphier-gpio";
- reg = <0x55000008 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port1x: gpio@55000010 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000010 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port2x: gpio@55000018 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000018 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port3x: gpio@55000020 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000020 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port4: gpio@55000028 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000028 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port5x: gpio@55000030 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000030 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port6x: gpio@55000038 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000038 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port7x: gpio@55000040 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000040 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port8x: gpio@55000048 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000048 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port9x: gpio@55000050 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000050 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port10x: gpio@55000058 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000058 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port12x: gpio@55000068 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000068 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port13x: gpio@55000070 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000070 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port14x: gpio@55000078 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000078 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port15x: gpio@55000080 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000080 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port16x: gpio@55000088 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000088 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port17x: gpio@550000a0 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x550000a0 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port18x: gpio@550000a8 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x550000a8 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port19x: gpio@550000b0 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x550000b0 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port20x: gpio@550000b8 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x550000b8 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port21x: gpio@550000c0 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x550000c0 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port22x: gpio@550000c8 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x550000c8 0x8>;
+ reg = <0x55000000 0x200>;
+ interrupt-parent = <&aidet>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
gpio-controller;
#gpio-cells = <2>;
- };
+ gpio-ranges = <&pinctrl 0 0 0>,
+ <&pinctrl 96 0 0>;
+ gpio-ranges-group-names = "gpio_range0",
+ "gpio_range1";
+ ngpios = <232>;
+ socionext,interrupt-ranges = <0 48 16>, <16 154 5>,
+ <21 217 3>;
+ };
+
+ audio@56000000 {
+ compatible = "socionext,uniphier-pxs2-aio";
+ reg = <0x56000000 0x80000>;
+ interrupts = <0 144 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ain1>,
+ <&pinctrl_ain2>,
+ <&pinctrl_ainiec1>,
+ <&pinctrl_aout2>,
+ <&pinctrl_aout3>,
+ <&pinctrl_aoutiec1>,
+ <&pinctrl_aoutiec2>;
+ clock-names = "aio";
+ clocks = <&sys_clk 40>;
+ reset-names = "aio";
+ resets = <&sys_rst 40>;
+ #sound-dai-cells = <1>;
+ socionext,syscon = <&soc_glue>;
+
+ i2s_port0: port@0 {
+ i2s_hdmi: endpoint {
+ };
+ };
- port23x: gpio@550000d0 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x550000d0 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
+ i2s_port1: port@1 {
+ i2s_line: endpoint {
+ };
+ };
- port24x: gpio@550000d8 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x550000d8 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
+ i2s_port2: port@2 {
+ i2s_aux: endpoint {
+ };
+ };
- port25x: gpio@550000e0 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x550000e0 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
+ spdif_port0: port@3 {
+ spdif_hiecout1: endpoint {
+ };
+ };
- port26x: gpio@550000e8 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x550000e8 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
+ spdif_port1: port@4 {
+ spdif_iecout1: endpoint {
+ };
+ };
- port27x: gpio@550000f0 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x550000f0 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
+ comp_spdif_port0: port@5 {
+ comp_spdif_hiecout1: endpoint {
+ };
+ };
- port28x: gpio@550000f8 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x550000f8 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
+ comp_spdif_port1: port@6 {
+ comp_spdif_iecout1: endpoint {
+ };
+ };
};
i2c0: i2c@58780000 {
interrupts = <0 41 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c0>;
- clocks = <&i2c_clk>;
+ clocks = <&peri_clk 4>;
+ resets = <&peri_rst 4>;
clock-frequency = <100000>;
};
interrupts = <0 42 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
- clocks = <&i2c_clk>;
+ clocks = <&peri_clk 5>;
+ resets = <&peri_rst 5>;
clock-frequency = <100000>;
};
interrupts = <0 43 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
- clocks = <&i2c_clk>;
+ clocks = <&peri_clk 6>;
+ resets = <&peri_rst 6>;
clock-frequency = <100000>;
};
interrupts = <0 44 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
- clocks = <&i2c_clk>;
+ clocks = <&peri_clk 7>;
+ resets = <&peri_rst 7>;
clock-frequency = <100000>;
};
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 45 4>;
- clocks = <&i2c_clk>;
+ clocks = <&peri_clk 8>;
+ resets = <&peri_rst 8>;
clock-frequency = <400000>;
};
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 25 4>;
- clocks = <&i2c_clk>;
+ clocks = <&peri_clk 9>;
+ resets = <&peri_rst 9>;
clock-frequency = <400000>;
};
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 26 4>;
- clocks = <&i2c_clk>;
+ clocks = <&peri_clk 10>;
+ resets = <&peri_rst 10>;
clock-frequency = <400000>;
};
pinctrl-0 = <&pinctrl_system_bus>;
};
- smpctrl@59800000 {
+ smpctrl@59801000 {
compatible = "socionext,uniphier-smpctrl";
reg = <0x59801000 0x400>;
};
sdctrl@59810000 {
compatible = "socionext,uniphier-pxs2-sdctrl",
"simple-mfd", "syscon";
- reg = <0x59810000 0x800>;
- u-boot,dm-pre-reloc;
+ reg = <0x59810000 0x400>;
sd_clk: clock {
compatible = "socionext,uniphier-pxs2-sd-clock";
sd-uhs-sdr50;
};
- soc-glue@5f800000 {
+ soc_glue: soc-glue@5f800000 {
compatible = "socionext,uniphier-pxs2-soc-glue",
"simple-mfd", "syscon";
reg = <0x5f800000 0x2000>;
- u-boot,dm-pre-reloc;
pinctrl: pinctrl {
compatible = "socionext,uniphier-pxs2-pinctrl";
- u-boot,dm-pre-reloc;
};
};
- aidet@5fc20000 {
- compatible = "simple-mfd", "syscon";
+ soc-glue@5f900000 {
+ compatible = "socionext,uniphier-pxs2-soc-glue-debug",
+ "simple-mfd";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x5f900000 0x2000>;
+
+ efuse@100 {
+ compatible = "socionext,uniphier-efuse";
+ reg = <0x100 0x28>;
+ };
+
+ efuse@200 {
+ compatible = "socionext,uniphier-efuse";
+ reg = <0x200 0x58>;
+ };
+ };
+
+ aidet: aidet@5fc20000 {
+ compatible = "socionext,uniphier-pxs2-aidet";
reg = <0x5fc20000 0x200>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
};
timer@60000200 {
sysctrl@61840000 {
compatible = "socionext,uniphier-pxs2-sysctrl",
"simple-mfd", "syscon";
- reg = <0x61840000 0x4000>;
+ reg = <0x61840000 0x10000>;
sys_clk: clock {
compatible = "socionext,uniphier-pxs2-clock";
compatible = "socionext,uniphier-pxs2-reset";
#reset-cells = <1>;
};
+
+ pvtctl: pvtctl {
+ compatible = "socionext,uniphier-pxs2-thermal";
+ interrupts = <0 3 4>;
+ #thermal-sensor-cells = <0>;
+ socionext,tmod-calibration = <0x0f86 0x6844>;
+ };
+ };
+
+ eth: ethernet@65000000 {
+ compatible = "socionext,uniphier-pxs2-ave4";
+ status = "disabled";
+ reg = <0x65000000 0x8500>;
+ interrupts = <0 66 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ether_rgmii>;
+ clock-names = "ether";
+ clocks = <&sys_clk 6>;
+ reset-names = "ether";
+ resets = <&sys_rst 6>;
+ phy-mode = "rgmii";
+ local-mac-address = [00 00 00 00 00 00];
+ socionext,syscon-phy-mode = <&soc_glue 0>;
+
+ mdio: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
};
usb0: usb@65b00000 {
compatible = "snps,dwc3";
reg = <0x65a00000 0x10000>;
interrupts = <0 134 4>;
+ dr_mode = "host";
tx-fifo-resize;
};
};
compatible = "snps,dwc3";
reg = <0x65c00000 0x10000>;
interrupts = <0 137 4>;
+ dr_mode = "host";
tx-fifo-resize;
};
};
nand: nand@68000000 {
- compatible = "socionext,denali-nand-v5b";
+ compatible = "socionext,uniphier-denali-nand-v5b";
status = "disabled";
reg-names = "nand_data", "denali_reg";
reg = <0x68000000 0x20>, <0x68100000 0x1000>;
interrupts = <0 65 4>;
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_nand>;
+ pinctrl-0 = <&pinctrl_nand2cs>;
clocks = <&sys_clk 2>;
- nand-ecc-strength = <8>;
+ resets = <&sys_rst 2>;
};
};
};
-/include/ "uniphier-pinctrl.dtsi"
+#include "uniphier-pinctrl.dtsi"
projects / u-boot / blobdiff