ARM: zynq: DT: Get rid of ps-clk-frequency

[u-boot] / arch / arm / dts / zynq-7000.dtsi

diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi
index 383ddd674b080bfe02a973efa5711de39656d0bf..095c0f67e1671a295e3339ab97800ad2e3e4865d 100644 (file)
--- a/arch/arm/dts/zynq-7000.dtsi
+++ b/arch/arm/dts/zynq-7000.dtsi
@@ -2,7 +2,7 @@
  * Xilinx Zynq 7000 DTSI
  * Describes the hardware common to all Zynq 7000-based boards.
  *
- * Copyright (C) 2013 Xilinx, Inc.
+ *  Copyright (C) 2011 - 2015 Xilinx
  *
  * SPDX-License-Identifier:    GPL-2.0+
  */
@@ -53,7 +53,7 @@
                regulator-always-on;
        };
 
-       amba {
+       amba: amba {
                compatible = "simple-bus";
                #address-cells = <1>;
                #size-cells = <1>;
@@ -127,7 +127,6 @@
                intc: interrupt-controller@f8f01000 {
                        compatible = "arm,cortex-a9-gic";
                        #interrupt-cells = <3>;
-                       #address-cells = <1>;
                        interrupt-controller;
                        reg = <0xF8F01000 0x1000>,
                              <0xF8F00100 0x100>;
@@ -198,6 +197,8 @@
                        interrupts = <0 22 4>;
                        clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;
                        clock-names = "pclk", "hclk", "tx_clk";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
                };
 
                gem1: ethernet@e000c000 {
@@ -207,6 +208,8 @@
                        interrupts = <0 45 4>;
                        clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>;
                        clock-names = "pclk", "hclk", "tx_clk";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
                };
 
                sdhci0: sdhci@e0100000 {
@@ -232,13 +235,12 @@
                slcr: slcr@f8000000 {
                        #address-cells = <1>;
                        #size-cells = <1>;
-                       compatible = "xlnx,zynq-slcr", "syscon";
+                       compatible = "xlnx,zynq-slcr", "syscon", "simple-bus";
                        reg = <0xF8000000 0x1000>;
                        ranges;
                        clkc: clkc@100 {
                                #clock-cells = <1>;
                                compatible = "xlnx,ps7-clkc";
-                               ps-clk-frequency = <33333333>;
                                fclk-enable = <0>;
                                clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
                                                "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
@@ -253,6 +255,12 @@
                                                "dbg_trc", "dbg_apb";
                                reg = <0x100 0x100>;
                        };
+
+                       pinctrl0: pinctrl@700 {
+                               compatible = "xlnx,pinctrl-zynq";
+                               reg = <0x700 0x200>;
+                               syscon = <&slcr>;
+                       };
                };
 
                dmac_s: dmac@f8003000 {
@@ -288,7 +296,7 @@
 
                ttc0: timer@f8001000 {
                        interrupt-parent = <&intc>;
-                       interrupts = < 0 10 4 0 11 4 0 12 4 >;
+                       interrupts = <0 10 4>, <0 11 4>, <0 12 4>;
                        compatible = "cdns,ttc";
                        clocks = <&clkc 6>;
                        reg = <0xF8001000 0x1000>;
@@ -296,7 +304,7 @@
 
                ttc1: timer@f8002000 {
                        interrupt-parent = <&intc>;
-                       interrupts = < 0 37 4 0 38 4 0 39 4 >;
+                       interrupts = <0 37 4>, <0 38 4>, <0 39 4>;
                        compatible = "cdns,ttc";
                        clocks = <&clkc 6>;
                        reg = <0xF8002000 0x1000>;