ARM: zynq: DT: Add missing interrupt for L2 pl310

[u-boot] / arch / arm / dts / zynq-7000.dtsi

diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi
index 276aa75097fcdea1da3b66a12af1aa3dcdb24ade..0b62cb093658a79de876e015985a7b92e9135103 100644 (file)
--- a/arch/arm/dts/zynq-7000.dtsi
+++ b/arch/arm/dts/zynq-7000.dtsi
@@ -2,7 +2,7 @@
  * Xilinx Zynq 7000 DTSI
  * Describes the hardware common to all Zynq 7000-based boards.
  *
- * Copyright (C) 2013 Xilinx, Inc.
+ *  Copyright (C) 2011 - 2015 Xilinx
  *
  * SPDX-License-Identifier:    GPL-2.0+
  */
@@ -53,7 +53,7 @@
                regulator-always-on;
        };
 
-       amba {
+       amba: amba {
                compatible = "simple-bus";
                #address-cells = <1>;
                #size-cells = <1>;
@@ -135,6 +135,7 @@
                L2: cache-controller@f8f02000 {
                        compatible = "arm,pl310-cache";
                        reg = <0xF8F02000 0x1000>;
+                       interrupts = <0 2 4>;
                        arm,data-latency = <3 2 2>;
                        arm,tag-latency = <2 2 2>;
                        cache-unified;
@@ -235,13 +236,12 @@
                slcr: slcr@f8000000 {
                        #address-cells = <1>;
                        #size-cells = <1>;
-                       compatible = "xlnx,zynq-slcr", "syscon";
+                       compatible = "xlnx,zynq-slcr", "syscon", "simple-bus";
                        reg = <0xF8000000 0x1000>;
                        ranges;
                        clkc: clkc@100 {
                                #clock-cells = <1>;
                                compatible = "xlnx,ps7-clkc";
-                               ps-clk-frequency = <33333333>;
                                fclk-enable = <0>;
                                clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
                                                "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
@@ -256,6 +256,12 @@
                                                "dbg_trc", "dbg_apb";
                                reg = <0x100 0x100>;
                        };
+
+                       pinctrl0: pinctrl@700 {
+                               compatible = "xlnx,pinctrl-zynq";
+                               reg = <0x700 0x200>;
+                               syscon = <&slcr>;
+                       };
                };
 
                dmac_s: dmac@f8003000 {