Merge branch 'master' of git://git.denx.de/u-boot

[u-boot] / arch / arm / dts / zynq-7000.dtsi

diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi
index 383ddd674b080bfe02a973efa5711de39656d0bf..b618a3f484f0e507948bdff1017cc01ec40a4e26 100644 (file)
--- a/arch/arm/dts/zynq-7000.dtsi
+++ b/arch/arm/dts/zynq-7000.dtsi
@@ -2,7 +2,7 @@
  * Xilinx Zynq 7000 DTSI
  * Describes the hardware common to all Zynq 7000-based boards.
  *
- * Copyright (C) 2013 Xilinx, Inc.
+ *  Copyright (C) 2011 - 2015 Xilinx
  *
  * SPDX-License-Identifier:    GPL-2.0+
  */
@@ -53,7 +53,8 @@
                regulator-always-on;
        };
 
-       amba {
+       amba: amba {
+               u-boot,dm-pre-reloc;
                compatible = "simple-bus";
                #address-cells = <1>;
                #size-cells = <1>;
@@ -95,8 +96,10 @@
                gpio0: gpio@e000a000 {
                        compatible = "xlnx,zynq-gpio-1.0";
                        #gpio-cells = <2>;
+                       #interrupt-cells = <2>;
                        clocks = <&clkc 42>;
                        gpio-controller;
+                       interrupt-controller;
                        interrupt-parent = <&intc>;
                        interrupts = <0 20 4>;
                        reg = <0xe000a000 0x1000>;
@@ -127,7 +130,6 @@
                intc: interrupt-controller@f8f01000 {
                        compatible = "arm,cortex-a9-gic";
                        #interrupt-cells = <3>;
-                       #address-cells = <1>;
                        interrupt-controller;
                        reg = <0xF8F01000 0x1000>,
                              <0xF8F00100 0x100>;
@@ -136,6 +138,7 @@
                L2: cache-controller@f8f02000 {
                        compatible = "arm,pl310-cache";
                        reg = <0xF8F02000 0x1000>;
+                       interrupts = <0 2 4>;
                        arm,data-latency = <3 2 2>;
                        arm,tag-latency = <2 2 2>;
                        cache-unified;
@@ -191,6 +194,18 @@
                        #size-cells = <0>;
                };
 
+               qspi: spi@e000d000 {
+                       clock-names = "ref_clk", "pclk";
+                       clocks = <&clkc 10>, <&clkc 43>;
+                       compatible = "xlnx,zynq-qspi-1.0";
+                       status = "disabled";
+                       interrupt-parent = <&intc>;
+                       interrupts = <0 19 4>;
+                       reg = <0xe000d000 0x1000>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+               };
+
                gem0: ethernet@e000b000 {
                        compatible = "cdns,zynq-gem", "cdns,gem";
                        reg = <0xe000b000 0x1000>;
@@ -198,6 +213,8 @@
                        interrupts = <0 22 4>;
                        clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;
                        clock-names = "pclk", "hclk", "tx_clk";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
                };
 
                gem1: ethernet@e000c000 {
@@ -207,6 +224,8 @@
                        interrupts = <0 45 4>;
                        clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>;
                        clock-names = "pclk", "hclk", "tx_clk";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
                };
 
                sdhci0: sdhci@e0100000 {
@@ -217,7 +236,7 @@
                        interrupt-parent = <&intc>;
                        interrupts = <0 24 4>;
                        reg = <0xe0100000 0x1000>;
-               } ;
+               };
 
                sdhci1: sdhci@e0101000 {
                        compatible = "arasan,sdhci-8.9a";
@@ -227,18 +246,17 @@
                        interrupt-parent = <&intc>;
                        interrupts = <0 47 4>;
                        reg = <0xe0101000 0x1000>;
-               } ;
+               };
 
                slcr: slcr@f8000000 {
                        #address-cells = <1>;
                        #size-cells = <1>;
-                       compatible = "xlnx,zynq-slcr", "syscon";
+                       compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd";
                        reg = <0xF8000000 0x1000>;
                        ranges;
                        clkc: clkc@100 {
                                #clock-cells = <1>;
                                compatible = "xlnx,ps7-clkc";
-                               ps-clk-frequency = <33333333>;
                                fclk-enable = <0>;
                                clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
                                                "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
@@ -253,6 +271,19 @@
                                                "dbg_trc", "dbg_apb";
                                reg = <0x100 0x100>;
                        };
+
+                       rstc: rstc@200 {
+                               compatible = "xlnx,zynq-reset";
+                               reg = <0x200 0x48>;
+                               #reset-cells = <1>;
+                               syscon = <&slcr>;
+                       };
+
+                       pinctrl0: pinctrl@700 {
+                               compatible = "xlnx,pinctrl-zynq";
+                               reg = <0x700 0x200>;
+                               syscon = <&slcr>;
+                       };
                };
 
                dmac_s: dmac@f8003000 {
@@ -275,7 +306,12 @@
 
                devcfg: devcfg@f8007000 {
                        compatible = "xlnx,zynq-devcfg-1.0";
+                       interrupt-parent = <&intc>;
+                       interrupts = <0 8 4>;
                        reg = <0xf8007000 0x100>;
+                       clocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>;
+                       clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3";
+                       syscon = <&slcr>;
                };
 
                global_timer: timer@f8f00200 {
@@ -288,7 +324,7 @@
 
                ttc0: timer@f8001000 {
                        interrupt-parent = <&intc>;
-                       interrupts = < 0 10 4 0 11 4 0 12 4 >;
+                       interrupts = <0 10 4>, <0 11 4>, <0 12 4>;
                        compatible = "cdns,ttc";
                        clocks = <&clkc 6>;
                        reg = <0xF8001000 0x1000>;
@@ -296,7 +332,7 @@
 
                ttc1: timer@f8002000 {
                        interrupt-parent = <&intc>;
-                       interrupts = < 0 37 4 0 38 4 0 39 4 >;
+                       interrupts = <0 37 4>, <0 38 4>, <0 39 4>;
                        compatible = "cdns,ttc";
                        clocks = <&clkc 6>;
                        reg = <0xF8002000 0x1000>;
@@ -304,11 +340,11 @@
 
                scutimer: timer@f8f00600 {
                        interrupt-parent = <&intc>;
-                       interrupts = < 1 13 0x301 >;
+                       interrupts = <1 13 0x301>;
                        compatible = "arm,cortex-a9-twd-timer";
-                       reg = < 0xf8f00600 0x20 >;
+                       reg = <0xf8f00600 0x20>;
                        clocks = <&clkc 4>;
-               } ;
+               };
 
                usb0: usb@e0002000 {
                        compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";