arm: zynq: Sync up licenses with mainline kernel

[u-boot] / arch / arm / dts / zynq-zc702.dts

diff --git a/arch/arm/dts/zynq-zc702.dts b/arch/arm/dts/zynq-zc702.dts
index 478e9fd4ef25c26adcc092bf25a9925c0bac4c00..b95c1608d2201a2cea2e1689256a3107bf6a1767 100644 (file)
--- a/arch/arm/dts/zynq-zc702.dts
+++ b/arch/arm/dts/zynq-zc702.dts
@@ -1,10 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
- * Xilinx ZC702 board DTS
- *
  *  Copyright (C) 2011 - 2015 Xilinx
  *  Copyright (C) 2012 National Instruments Corp.
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 /dts-v1/;
 #include "zynq-7000.dtsi"
@@ -40,14 +37,14 @@
                        label = "sw14";
                        gpios = <&gpio0 12 0>;
                        linux,code = <108>; /* down */
-                       gpio-key,wakeup;
+                       wakeup-source;
                        autorepeat;
                };
                sw13 {
                        label = "sw13";
                        gpios = <&gpio0 14 0>;
                        linux,code = <103>; /* up */
-                       gpio-key,wakeup;
+                       wakeup-source;
                        autorepeat;
                };
        };
@@ -96,6 +93,7 @@
 
        ethernet_phy: ethernet-phy@7 {
                reg = <7>;
+               device_type = "ethernet-phy";
        };
 };
 
@@ -107,8 +105,11 @@
 &i2c0 {
        status = "okay";
        clock-frequency = <400000>;
-       pinctrl-names = "default";
+       pinctrl-names = "default", "gpio";
        pinctrl-0 = <&pinctrl_i2c0_default>;
+       pinctrl-1 = <&pinctrl_i2c0_gpio>;
+       scl-gpios = <&gpio0 50 0>;
+       sda-gpios = <&gpio0 51 0>;
 
        i2cswitch@74 {
                compatible = "nxp,pca9548";
@@ -299,6 +300,19 @@
                };
        };
 
+       pinctrl_i2c0_gpio: i2c0-gpio {
+               mux {
+                       groups = "gpio0_50_grp", "gpio0_51_grp";
+                       function = "gpio0";
+               };
+
+               conf {
+                       groups = "gpio0_50_grp", "gpio0_51_grp";
+                       slew-rate = <0>;
+                       io-standard = <1>;
+               };
+       };
+
        pinctrl_sdhci0_default: sdhci0-default {
                mux {
                        groups = "sdio0_2_grp";