]> git.sur5r.net Git - u-boot/blobdiff - arch/arm/dts/zynq-zc702.dts
arm: zynq: Sync up licenses with mainline kernel
[u-boot] / arch / arm / dts / zynq-zc702.dts
index 6691a8de247d282118cf9bc16c37d2bf024f9b0f..b95c1608d2201a2cea2e1689256a3107bf6a1767 100644 (file)
@@ -1,10 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
- * Xilinx ZC702 board DTS
- *
  *  Copyright (C) 2011 - 2015 Xilinx
  *  Copyright (C) 2012 National Instruments Corp.
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 /dts-v1/;
 #include "zynq-7000.dtsi"
                ethernet0 = &gem0;
                i2c0 = &i2c0;
                serial0 = &uart1;
+               spi0 = &qspi;
+               mmc0 = &sdhci0;
        };
 
-       memory {
+       memory@0 {
                device_type = "memory";
                reg = <0x0 0x40000000>;
        };
 
        chosen {
-               bootargs = "earlyprintk";
+               bootargs = "";
                stdout-path = "serial0:115200n8";
        };
 
                        label = "sw14";
                        gpios = <&gpio0 12 0>;
                        linux,code = <108>; /* down */
-                       gpio-key,wakeup;
+                       wakeup-source;
                        autorepeat;
                };
                sw13 {
                        label = "sw13";
                        gpios = <&gpio0 14 0>;
                        linux,code = <103>; /* up */
-                       gpio-key,wakeup;
+                       wakeup-source;
                        autorepeat;
                };
        };
        phy-handle = <&ethernet_phy>;
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_gem0_default>;
+       phy-reset-gpio = <&gpio0 11 0>;
+       phy-reset-active-low;
 
        ethernet_phy: ethernet-phy@7 {
                reg = <7>;
+               device_type = "ethernet-phy";
        };
 };
 
 &i2c0 {
        status = "okay";
        clock-frequency = <400000>;
-       pinctrl-names = "default";
+       pinctrl-names = "default", "gpio";
        pinctrl-0 = <&pinctrl_i2c0_default>;
+       pinctrl-1 = <&pinctrl_i2c0_gpio>;
+       scl-gpios = <&gpio0 50 0>;
+       sda-gpios = <&gpio0 51 0>;
 
        i2cswitch@74 {
                compatible = "nxp,pca9548";
                        };
                };
 
+               i2c@1 {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       reg = <1>;
+                       adv7511: hdmi-tx@39 {
+                               compatible = "adi,adv7511";
+                               reg = <0x39>;
+                               adi,input-depth = <8>;
+                               adi,input-colorspace = "yuv422";
+                               adi,input-clock = "1x";
+                               adi,input-style = <3>;
+                               adi,input-justification = "right";
+                       };
+               };
+
                i2c@2 {
                        #address-cells = <1>;
                        #size-cells = <0>;
                };
        };
 
+       pinctrl_i2c0_gpio: i2c0-gpio {
+               mux {
+                       groups = "gpio0_50_grp", "gpio0_51_grp";
+                       function = "gpio0";
+               };
+
+               conf {
+                       groups = "gpio0_50_grp", "gpio0_51_grp";
+                       slew-rate = <0>;
+                       io-standard = <1>;
+               };
+       };
+
        pinctrl_sdhci0_default: sdhci0-default {
                mux {
                        groups = "sdio0_2_grp";
        };
 };
 
+&qspi {
+       u-boot,dm-pre-reloc;
+       status = "okay";
+};
+
 &sdhci0 {
+       u-boot,dm-pre-reloc;
        status = "okay";
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_sdhci0_default>;
 };
 
 &uart1 {
+       u-boot,dm-pre-reloc;
        status = "okay";
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_uart1_default>;