arm: zynq: Sync up licenses with mainline kernel

[u-boot] / arch / arm / dts / zynq-zed.dts

diff --git a/arch/arm/dts/zynq-zed.dts b/arch/arm/dts/zynq-zed.dts
index 91a5deba4a9f7059f56fa9dc1b6ecd72b526fffe..24eccf1633d8bc462e1888a3a35d71cb492e57a4 100644 (file)
--- a/arch/arm/dts/zynq-zed.dts
+++ b/arch/arm/dts/zynq-zed.dts
@@ -1,14 +1,70 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
- * Xilinx ZED board DTS
- *
- * Copyright (C) 2013 Xilinx, Inc.
- *
- * SPDX-License-Identifier:    GPL-2.0+
+ *  Copyright (C) 2011 - 2015 Xilinx
+ *  Copyright (C) 2012 National Instruments Corp.
  */
 /dts-v1/;
 #include "zynq-7000.dtsi"
 
 / {
-       model = "Zynq ZED Board";
+       model = "Zynq Zed Development Board";
        compatible = "xlnx,zynq-zed", "xlnx,zynq-7000";
+
+       aliases {
+               ethernet0 = &gem0;
+               serial0 = &uart1;
+               spi0 = &qspi;
+               mmc0 = &sdhci0;
+       };
+
+       memory@0 {
+               device_type = "memory";
+               reg = <0x0 0x20000000>;
+       };
+
+       chosen {
+               bootargs = "";
+               stdout-path = "serial0:115200n8";
+       };
+
+       usb_phy0: phy0 {
+               compatible = "usb-nop-xceiv";
+               #phy-cells = <0>;
+       };
+};
+
+&clkc {
+       ps-clk-frequency = <33333333>;
+};
+
+&gem0 {
+       status = "okay";
+       phy-mode = "rgmii-id";
+       phy-handle = <&ethernet_phy>;
+
+       ethernet_phy: ethernet-phy@0 {
+               reg = <0>;
+               device_type = "ethernet-phy";
+       };
+};
+
+&qspi {
+       u-boot,dm-pre-reloc;
+       status = "okay";
+};
+
+&sdhci0 {
+       u-boot,dm-pre-reloc;
+       status = "okay";
+};
+
+&uart1 {
+       u-boot,dm-pre-reloc;
+       status = "okay";
+};
+
+&usb0 {
+       status = "okay";
+       dr_mode = "host";
+       usb-phy = <&usb_phy0>;
 };