at91: Add support for the AT91 slow clock controller

[u-boot] / arch / arm / imx-common / cpu.c

diff --git a/arch/arm/imx-common/cpu.c b/arch/arm/imx-common/cpu.c
index 38cd0c8280717f1b85e76d6ba586e322dfddc5d5..42231872611caddf50b165fd55e066e67009141a 100644 (file)
--- a/arch/arm/imx-common/cpu.c
+++ b/arch/arm/imx-common/cpu.c
@@ -46,13 +46,28 @@ static char *get_reset_cause(void)
        case 0x00008:
                return "IPP USER";
        case 0x00010:
+#ifdef CONFIG_MX7
+               return "WDOG1";
+#else
                return "WDOG";
+#endif
        case 0x00020:
                return "JTAG HIGH-Z";
        case 0x00040:
                return "JTAG SW";
+       case 0x00080:
+               return "WDOG3";
+#ifdef CONFIG_MX7
+       case 0x00100:
+               return "WDOG4";
+       case 0x00200:
+               return "TEMPSENSE";
+#else
+       case 0x00100:
+               return "TEMPSENSE";
        case 0x10000:
                return "WARM BOOT";
+#endif
        default:
                return "unknown reset";
        }
@@ -122,6 +137,10 @@ unsigned imx_ddr_size(void)
 const char *get_imx_type(u32 imxtype)
 {
        switch (imxtype) {
+       case MXC_CPU_MX7S:
+               return "7S";    /* Single-core version of the mx7 */
+       case MXC_CPU_MX7D:
+               return "7D";    /* Dual-core version of the mx7 */
        case MXC_CPU_MX6QP:
                return "6QP";   /* Quad-Plus version of the mx6 */
        case MXC_CPU_MX6DP:
@@ -203,9 +222,9 @@ int print_cpuinfo(void)
                if (!ret)
                        printf(" at %dC\n", cpu_tmp);
                else
-                       puts(" - invalid sensor data\n");
+                       debug(" - invalid sensor data\n");
        } else {
-               puts(" - invalid sensor device\n");
+               debug(" - invalid sensor device\n");
        }
 #endif
 
@@ -236,6 +255,7 @@ int cpu_mmc_init(bd_t *bis)
 }
 #endif
 
+#ifndef CONFIG_MX7
 u32 get_ahb_clk(void)
 {
        struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
@@ -247,6 +267,7 @@ u32 get_ahb_clk(void)
 
        return get_periph_clk() / (ahb_podf + 1);
 }
+#endif
 
 void arch_preboot_os(void)
 {
@@ -260,6 +281,9 @@ void arch_preboot_os(void)
        /* disable video before launching O/S */
        ipuv3_fb_shutdown();
 #endif
+#if defined(CONFIG_VIDEO_MXS)
+       lcdif_power_down();
+#endif
 }
 
 void set_chipselect_size(int const cs_size)