ARMv8: fix bug for flush data cache by set/way

[u-boot] / arch / arm / imx-common / cpu.c

diff --git a/arch/arm/imx-common/cpu.c b/arch/arm/imx-common/cpu.c
index a9b86c1173203a3bd8740a5e5b08fa299e8e8194..a77c4decc960eb2b08767af005d69881d58cb41f 100644 (file)
--- a/arch/arm/imx-common/cpu.c
+++ b/arch/arm/imx-common/cpu.c
@@ -4,23 +4,7 @@
  *
  * (C) Copyright 2009 Freescale Semiconductor, Inc.
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
@@ -67,9 +51,9 @@ char *get_reset_cause(void)
 
 #if defined(CONFIG_MX53) || defined(CONFIG_MX6)
 #if defined(CONFIG_MX53)
-#define MEMCTL_BASE    ESDCTL_BASE_ADDR;
+#define MEMCTL_BASE    ESDCTL_BASE_ADDR
 #else
-#define MEMCTL_BASE    MMDC_P0_BASE_ADDR;
+#define MEMCTL_BASE    MMDC_P0_BASE_ADDR
 #endif
 static const unsigned char col_lookup[] = {9, 10, 11, 8, 12, 9, 9, 9};
 static const unsigned char bank_lookup[] = {3, 2};
@@ -122,6 +106,8 @@ const char *get_imx_type(u32 imxtype)
        switch (imxtype) {
        case MXC_CPU_MX6Q:
                return "6Q";    /* Quad-core version of the mx6 */
+       case MXC_CPU_MX6D:
+               return "6D";    /* Dual-core version of the mx6 */
        case MXC_CPU_MX6DL:
                return "6DL";   /* Dual Lite version of the mx6 */
        case MXC_CPU_MX6SOLO: