at91: Add support for the AT91 slow clock controller

[u-boot] / arch / arm / imx-common / init.c

diff --git a/arch/arm/imx-common/init.c b/arch/arm/imx-common/init.c
index f7ed038d8e82dbc5bfef693921314dca06b2c76d..15dab1d904239accc3676956ec5a8acbf3d8e444 100644 (file)
--- a/arch/arm/imx-common/init.c
+++ b/arch/arm/imx-common/init.c
@@ -13,16 +13,11 @@
 
 void init_aips(void)
 {
-       struct aipstz_regs *aips1, *aips2;
-#ifdef CONFIG_MX6SX
-       struct aipstz_regs *aips3;
-#endif
+       struct aipstz_regs *aips1, *aips2, *aips3;
 
        aips1 = (struct aipstz_regs *)AIPS1_BASE_ADDR;
        aips2 = (struct aipstz_regs *)AIPS2_BASE_ADDR;
-#ifdef CONFIG_MX6SX
        aips3 = (struct aipstz_regs *)AIPS3_BASE_ADDR;
-#endif
 
        /*
         * Set all MPROTx to be non-bufferable, trusted for R/W,
@@ -49,24 +44,45 @@ void init_aips(void)
        writel(0x00000000, &aips2->opacr3);
        writel(0x00000000, &aips2->opacr4);
 
-#ifdef CONFIG_MX6SX
-       /*
-        * Set all MPROTx to be non-bufferable, trusted for R/W,
-        * not forced to user-mode.
-        */
-       writel(0x77777777, &aips3->mprot0);
-       writel(0x77777777, &aips3->mprot1);
+       if (is_cpu_type(MXC_CPU_MX6SX) || is_soc_type(MXC_SOC_MX7)) {
+               /*
+                * Set all MPROTx to be non-bufferable, trusted for R/W,
+                * not forced to user-mode.
+                */
+               writel(0x77777777, &aips3->mprot0);
+               writel(0x77777777, &aips3->mprot1);
 
-       /*
-        * Set all OPACRx to be non-bufferable, not require
-        * supervisor privilege level for access,allow for
-        * write access and untrusted master access.
-        */
-       writel(0x00000000, &aips3->opacr0);
-       writel(0x00000000, &aips3->opacr1);
-       writel(0x00000000, &aips3->opacr2);
-       writel(0x00000000, &aips3->opacr3);
-       writel(0x00000000, &aips3->opacr4);
+               /*
+                * Set all OPACRx to be non-bufferable, not require
+                * supervisor privilege level for access,allow for
+                * write access and untrusted master access.
+                */
+               writel(0x00000000, &aips3->opacr0);
+               writel(0x00000000, &aips3->opacr1);
+               writel(0x00000000, &aips3->opacr2);
+               writel(0x00000000, &aips3->opacr3);
+               writel(0x00000000, &aips3->opacr4);
+       }
+}
+
+void imx_set_wdog_powerdown(bool enable)
+{
+       struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
+       struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
+       struct wdog_regs *wdog3 = (struct wdog_regs *)WDOG3_BASE_ADDR;
+#ifdef CONFIG_MX7D
+       struct wdog_regs *wdog4 = (struct wdog_regs *)WDOG4_BASE_ADDR;
+#endif
+
+       /* Write to the PDE (Power Down Enable) bit */
+       writew(enable, &wdog1->wmcr);
+       writew(enable, &wdog2->wmcr);
+
+       if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) ||
+                       is_soc_type(MXC_SOC_MX7))
+               writew(enable, &wdog3->wmcr);
+#ifdef CONFIG_MX7D
+       writew(enable, &wdog4->wmcr);
 #endif
 }
 
@@ -86,6 +102,7 @@ void init_src(void)
        writel(val, &src_regs->scr);
 }
 
+#ifdef CONFIG_CMD_BMODE
 void boot_mode_apply(unsigned cfg_val)
 {
        unsigned reg;
@@ -98,3 +115,4 @@ void boot_mode_apply(unsigned cfg_val)
                reg &= ~(1 << 28);
        writel(reg, &psrc->gpr10);
 }
+#endif