writel(0x00000000, &aips2->opacr3);
writel(0x00000000, &aips2->opacr4);
- if (is_cpu_type(MXC_CPU_MX6SX) || is_soc_type(MXC_SOC_MX7))
- {
+ if (is_mx6ull() || is_mx6sx() || is_mx7()) {
/*
* Set all MPROTx to be non-bufferable, trusted for R/W,
* not forced to user-mode.
}
}
+void imx_set_wdog_powerdown(bool enable)
+{
+ struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
+ struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
+ struct wdog_regs *wdog3 = (struct wdog_regs *)WDOG3_BASE_ADDR;
+#ifdef CONFIG_MX7D
+ struct wdog_regs *wdog4 = (struct wdog_regs *)WDOG4_BASE_ADDR;
+#endif
+
+ /* Write to the PDE (Power Down Enable) bit */
+ writew(enable, &wdog1->wmcr);
+ writew(enable, &wdog2->wmcr);
+
+ if (is_mx6sx() || is_mx6ul() || is_mx7())
+ writew(enable, &wdog3->wmcr);
+#ifdef CONFIG_MX7D
+ writew(enable, &wdog4->wmcr);
+#endif
+}
+
#define SRC_SCR_WARM_RESET_ENABLE 0
void init_src(void)
writel(val, &src_regs->scr);
}
+#ifdef CONFIG_CMD_BMODE
void boot_mode_apply(unsigned cfg_val)
{
unsigned reg;
reg &= ~(1 << 28);
writel(reg, &psrc->gpr10);
}
+#endif