mmc: fsl_esdhc: drop CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT

[u-boot] / arch / arm / imx-common / iomux-v3.c

diff --git a/arch/arm/imx-common/iomux-v3.c b/arch/arm/imx-common/iomux-v3.c
index b59b802830677b240af7ce915394b41a8a1a1831..c9a3bf29a525e626f096a9bc6ccc37631f47d4ca 100644 (file)
--- a/arch/arm/imx-common/iomux-v3.c
+++ b/arch/arm/imx-common/iomux-v3.c
@@ -12,6 +12,7 @@
 #include <asm/io.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/imx-common/iomux-v3.h>
+#include <asm/imx-common/sys_proto.h>
 
 static void *base = (void *)IOMUXC_BASE_ADDR;
 
@@ -30,7 +31,36 @@ void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad)
                (pad & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT;
        u32 pad_ctrl = (pad & MUX_PAD_CTRL_MASK) >> MUX_PAD_CTRL_SHIFT;
 
-       if (mux_ctrl_ofs)
+#if defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL)
+       /* Check whether LVE bit needs to be set */
+       if (pad_ctrl & PAD_CTL_LVE) {
+               pad_ctrl &= ~PAD_CTL_LVE;
+               pad_ctrl |= PAD_CTL_LVE_BIT;
+       }
+#endif
+
+#ifdef CONFIG_IOMUX_LPSR
+       u32 lpsr = (pad & MUX_MODE_LPSR) >> MUX_MODE_SHIFT;
+
+#ifdef CONFIG_MX7
+       if (lpsr == IOMUX_CONFIG_LPSR) {
+               base = (void *)IOMUXC_LPSR_BASE_ADDR;
+               mux_mode &= ~IOMUX_CONFIG_LPSR;
+               /* set daisy chain sel_input */
+               if (sel_input_ofs)
+                       sel_input_ofs += IOMUX_LPSR_SEL_INPUT_OFS;
+       }
+#else
+       if (is_mx6ull() || is_mx6sll()) {
+               if (lpsr == IOMUX_CONFIG_LPSR) {
+                       base = (void *)IOMUXC_SNVS_BASE_ADDR;
+                       mux_mode &= ~IOMUX_CONFIG_LPSR;
+               }
+       }
+#endif
+#endif
+
+       if (is_mx7() || is_mx6ull() || is_mx6sll() || mux_ctrl_ofs)
                __raw_writel(mux_mode, base + mux_ctrl_ofs);
 
        if (sel_input_ofs)
@@ -43,15 +73,77 @@ void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad)
 #else
        if (!(pad_ctrl & NO_PAD_CTRL) && pad_ctrl_ofs)
                __raw_writel(pad_ctrl, base + pad_ctrl_ofs);
+#if defined(CONFIG_MX6SLL)
+       else if ((pad_ctrl & NO_PAD_CTRL) && pad_ctrl_ofs)
+               clrbits_le32(base + pad_ctrl_ofs, PAD_CTL_IPD_BIT);
 #endif
+#endif
+
+#ifdef CONFIG_IOMUX_LPSR
+       if (lpsr == IOMUX_CONFIG_LPSR)
+               base = (void *)IOMUXC_BASE_ADDR;
+#endif
+
 }
 
+/* configures a list of pads within declared with IOMUX_PADS macro */
 void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list,
                                      unsigned count)
 {
        iomux_v3_cfg_t const *p = pad_list;
+       int stride;
        int i;
 
-       for (i = 0; i < count; i++)
-               imx_iomux_v3_setup_pad(*p++);
+#if defined(CONFIG_MX6QDL)
+       stride = 2;
+       if (!is_mx6dq() && !is_mx6dqp())
+               p += 1;
+#else
+       stride = 1;
+#endif
+       for (i = 0; i < count; i++) {
+               imx_iomux_v3_setup_pad(*p);
+               p += stride;
+       }
+}
+
+void imx_iomux_set_gpr_register(int group, int start_bit,
+                                       int num_bits, int value)
+{
+       int i = 0;
+       u32 reg;
+       reg = readl(base + group * 4);
+       while (num_bits) {
+               reg &= ~(1<<(start_bit + i));
+               i++;
+               num_bits--;
+       }
+       reg |= (value << start_bit);
+       writel(reg, base + group * 4);
 }
+
+#ifdef CONFIG_IOMUX_SHARE_CONF_REG
+void imx_iomux_gpio_set_direction(unsigned int gpio,
+                               unsigned int direction)
+{
+       u32 reg;
+       /*
+        * Only on Vybrid the input/output buffer enable flags
+        * are part of the shared mux/conf register.
+        */
+       reg = readl(base + (gpio << 2));
+
+       if (direction)
+               reg |= 0x2;
+       else
+               reg &= ~0x2;
+
+       writel(reg, base + (gpio << 2));
+}
+
+void imx_iomux_gpio_get_function(unsigned int gpio, u32 *gpio_state)
+{
+       *gpio_state = readl(base + (gpio << 2)) &
+               ((0X07 << PAD_MUX_MODE_SHIFT) | PAD_CTL_OBE_IBE_ENABLE);
+}
+#endif