imx: mx7: default enable MDIO open drain

[u-boot] / arch / arm / include / asm / arch-am33xx / clock.h

diff --git a/arch/arm/include/asm/arch-am33xx/clock.h b/arch/arm/include/asm/arch-am33xx/clock.h
index 0d4b9ae6f8a28b1c536614defaeda67f7b36fe88..a6d2419fb843de713880e16b09fe7e57ad43a090 100644 (file)
--- a/arch/arm/include/asm/arch-am33xx/clock.h
+++ b/arch/arm/include/asm/arch-am33xx/clock.h
@@ -13,6 +13,10 @@
 
 #include <asm/arch/clocks_am33xx.h>
 
+#ifdef CONFIG_TI81XX
+#include <asm/arch/clock_ti81xx.h>
+#endif
+
 #define LDELAY 1000000
 
 /*CM_<clock_domain>__CLKCTRL */
@@ -38,6 +42,8 @@
 #define MODULE_CLKCTRL_IDLEST_DISABLED         3
 
 /* CM_CLKMODE_DPLL */
+#define CM_CLKMODE_DPLL_SSC_EN_SHIFT           12
+#define CM_CLKMODE_DPLL_SSC_EN_MASK            (1 << 12)
 #define CM_CLKMODE_DPLL_REGM4XEN_SHIFT         11
 #define CM_CLKMODE_DPLL_REGM4XEN_MASK          (1 << 11)
 #define CM_CLKMODE_DPLL_LPMODE_EN_SHIFT                10
@@ -94,17 +100,18 @@ extern const struct dpll_regs dpll_mpu_regs;
 extern const struct dpll_regs dpll_core_regs;
 extern const struct dpll_regs dpll_per_regs;
 extern const struct dpll_regs dpll_ddr_regs;
-extern const struct dpll_params dpll_mpu;
-extern const struct dpll_params dpll_core;
-extern const struct dpll_params dpll_per;
-extern const struct dpll_params dpll_ddr;
 
 extern struct cm_wkuppll *const cmwkup;
 
+const struct dpll_params *get_dpll_mpu_params(void);
+const struct dpll_params *get_dpll_core_params(void);
+const struct dpll_params *get_dpll_per_params(void);
 const struct dpll_params *get_dpll_ddr_params(void);
+void scale_vcores(void);
 void do_setup_dpll(const struct dpll_regs *, const struct dpll_params *);
 void prcm_init(void);
 void enable_basic_clocks(void);
 void do_enable_clocks(u32 *const *, u32 *const *, u8);
+void do_disable_clocks(u32 *const *, u32 *const *, u8);
 
 #endif