am335x: fix GPMC config for NAND and NOR SPL boot

[u-boot] / arch / arm / include / asm / arch-am33xx / hardware.h

diff --git a/arch/arm/include/asm/arch-am33xx/hardware.h b/arch/arm/include/asm/arch-am33xx/hardware.h
index fa0bbda8f3c7846b8db88592ccaca7e0369c820b..ee5fce0da1caef5677d66d565c66d0b956beb61e 100644 (file)
--- a/arch/arm/include/asm/arch-am33xx/hardware.h
+++ b/arch/arm/include/asm/arch-am33xx/hardware.h
@@ -15,6 +15,8 @@
 #include <asm/arch/omap.h>
 #ifdef CONFIG_AM33XX
 #include <asm/arch/hardware_am33xx.h>
+#elif defined(CONFIG_TI816X)
+#include <asm/arch/hardware_ti816x.h>
 #elif defined(CONFIG_TI814X)
 #include <asm/arch/hardware_ti814x.h>
 #elif defined(CONFIG_AM43XX)
@@ -53,25 +55,18 @@
 #define CM_CEFUSE                      0x44E00A00
 #define PRM_DEVICE                     0x44E00F00
 
-/* VTP Base address */
-#define VTP1_CTRL_ADDR                 0x48140E10
-
 /* DDR Base address */
 #define DDR_CTRL_ADDR                  0x44E10E04
 #define DDR_CONTROL_BASE_ADDR          0x44E11404
-#define DDR_PHY_CMD_ADDR2              0x47C0C800
-#define DDR_PHY_DATA_ADDR2             0x47C0C8C8
 
 /* UART */
 #define DEFAULT_UART_BASE              UART0_BASE
 
-#define DDRPHY_0_CONFIG_BASE           (CTRL_BASE + 0x1400)
-#define DDRPHY_CONFIG_BASE             DDRPHY_0_CONFIG_BASE
-
 /* GPMC Base address */
 #define GPMC_BASE                      0x50000000
 
 /* CPSW Config space */
 #define CPSW_BASE                      0x4A100000
 
+int clk_get(int clk);
 #endif /* __AM33XX_HARDWARE_H */