/* PRCM Base Address */
#define PRCM_BASE 0x44E00000
+#define CM_PER 0x44E00000
+#define CM_WKUP 0x44E00400
+
+#define PRM_RSTCTRL (PRCM_BASE + 0x0F00)
+#define PRM_RSTST (PRM_RSTCTRL + 8)
/* VTP Base address */
#define VTP0_CTRL_ADDR 0x44E10E0C
+#define VTP1_CTRL_ADDR 0x48140E10
/* DDR Base address */
#define DDR_PHY_CMD_ADDR 0x44E12000
#define DDR_PHY_DATA_ADDR 0x44E120C8
+#define DDR_PHY_CMD_ADDR2 0x47C0C800
+#define DDR_PHY_DATA_ADDR2 0x47C0C8C8
#define DDR_DATA_REGS_NR 2
+#define DDRPHY_0_CONFIG_BASE (CTRL_BASE + 0x1400)
+#define DDRPHY_CONFIG_BASE DDRPHY_0_CONFIG_BASE
+
/* CPSW Config space */
#define CPSW_MDIO_BASE 0x4A101000
/* RTC base address */
#define RTC_BASE 0x44E3E000
+/* OTG */
+#define USB0_OTG_BASE 0x47401000
+#define USB1_OTG_BASE 0x47401800
+
#endif /* __AM33XX_HARDWARE_AM33XX_H */