Merge branch 'master' of git://git.denx.de/u-boot-avr32

[u-boot] / arch / arm / include / asm / arch-am33xx / hardware_am33xx.h

diff --git a/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h b/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h
index fa02f195ff7790a3b00bf762861b27bed783b728..d1aed58503fcd8ccb8ff313168650e31e0f188fd 100644 (file)
--- a/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h
+++ b/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h
@@ -5,15 +5,7 @@
  *
  * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
  *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
- * GNU General Public License for more details.
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #ifndef __AM33XX_HARDWARE_AM33XX_H
@@ -36,19 +28,44 @@
 
 /* PRCM Base Address */
 #define PRCM_BASE                      0x44E00000
+#define CM_PER                         0x44E00000
+#define CM_WKUP                                0x44E00400
+#define CM_DPLL                                0x44E00500
+#define CM_RTC                         0x44E00800
+
+#define PRM_RSTCTRL                    (PRCM_BASE + 0x0F00)
+#define PRM_RSTST                      (PRM_RSTCTRL + 8)
 
 /* VTP Base address */
 #define VTP0_CTRL_ADDR                 0x44E10E0C
+#define VTP1_CTRL_ADDR                 0x48140E10
+#define PRM_DEVICE_INST                        0x44E00F00
 
 /* DDR Base address */
 #define DDR_PHY_CMD_ADDR               0x44E12000
 #define DDR_PHY_DATA_ADDR              0x44E120C8
+#define DDR_PHY_CMD_ADDR2              0x47C0C800
+#define DDR_PHY_DATA_ADDR2             0x47C0C8C8
 #define DDR_DATA_REGS_NR               2
 
+#define DDRPHY_0_CONFIG_BASE           (CTRL_BASE + 0x1400)
+#define DDRPHY_CONFIG_BASE             DDRPHY_0_CONFIG_BASE
+
 /* CPSW Config space */
 #define CPSW_MDIO_BASE                 0x4A101000
 
 /* RTC base address */
 #define RTC_BASE                       0x44E3E000
 
+/* OTG */
+#define USB0_OTG_BASE                  0x47401000
+#define USB1_OTG_BASE                  0x47401800
+
+/* LCD Controller */
+#define LCD_CNTL_BASE                  0x4830E000
+
+/* PWMSS */
+#define PWMSS0_BASE                    0x48300000
+#define AM33XX_ECAP0_BASE              0x48300100
+
 #endif /* __AM33XX_HARDWARE_AM33XX_H */