Merge git://git.denx.de/u-boot-mpc85xx

[u-boot] / arch / arm / include / asm / arch-am33xx / hardware_am43xx.h

diff --git a/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h b/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h
index 15399dcc747df4742510ef6a2e9006d604b62b67..a7da6b5cfde64e23f59b9e3e348bf375716bf5c2 100644 (file)
--- a/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h
+++ b/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h
@@ -13,6 +13,9 @@
 
 /* Module base addresses */
 
+/* L3 Fast Configuration Bandwidth Limiter Base Address */
+#define L3F_CFG_BWLIMITER              0x44005200
+
 /* UART Base Address */
 #define UART0_BASE                     0x44E09000
 
@@ -40,6 +43,11 @@
 #define VTP0_CTRL_ADDR                 0x44E10E0C
 #define VTP1_CTRL_ADDR                 0x48140E10
 
+/* USB CTRL Base Address */
+#define USB1_CTRL                      0x44e10628
+#define USB1_CTRL_CM_PWRDN             BIT(0)
+#define USB1_CTRL_OTG_PWRDN            BIT(1)
+
 /* DDR Base address */
 #define DDR_PHY_CMD_ADDR               0x44E12000
 #define DDR_PHY_DATA_ADDR              0x44E120C8
@@ -53,6 +61,15 @@
 /* RTC base address */
 #define RTC_BASE                       0x44E3E000
 
+/* USB OTG */
+#define USB_OTG_SS1_BASE               0x48390000
+#define USB_OTG_SS1_GLUE_BASE          0x48380000
+#define USB2_PHY1_POWER                        0x44E10620
+
+#define USB_OTG_SS2_BASE               0x483D0000
+#define USB_OTG_SS2_GLUE_BASE          0x483C0000
+#define USB2_PHY2_POWER                        0x44E10628
+
 /* USB Clock Control */
 #define PRM_PER_USB_OTG_SS0_CLKCTRL (CM_PER + 0x260)
 #define PRM_PER_USB_OTG_SS1_CLKCTRL (CM_PER + 0x268)
@@ -63,6 +80,10 @@
 #define PRM_PER_USBPHYOCP2SCP1_CLKCTRL (CM_PER + 0x5c0)
 #define USBPHYOCPSCP_MODULE_EN (1 << 1)
 #define CM_DEVICE_INST                 0x44df4100
+#define PRM_DEVICE_INST                        0x44df4000
+
+#define        USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960   (1 << 8)
+#define        USBPHY0_CLKCTRL_OPTFCLKEN_CLK32K        (1 << 8)
 
 /* Control status register */
 #define CTRL_CRYSTAL_FREQ_SRC_MASK             (1 << 31)
@@ -77,4 +98,7 @@
 
 #define NUM_CRYSTAL_FREQ                       0x4
 
+/* EDMA3 Base Address */
+#define EDMA3_BASE                             0x49000000
+
 #endif /* __AM43XX_HARDWARE_AM43XX_H */