Add GPL-2.0+ SPDX-License-Identifier to source files

[u-boot] / arch / arm / include / asm / arch-at91 / at91_pmc.h

diff --git a/arch/arm/include/asm/arch-at91/at91_pmc.h b/arch/arm/include/asm/arch-at91/at91_pmc.h
index 5b1a85d051479416f8400ac96193ace31635b902..003920cd84bf69034596c25878bcd6864b5969bc 100644 (file)
--- a/arch/arm/include/asm/arch-at91/at91_pmc.h
+++ b/arch/arm/include/asm/arch-at91/at91_pmc.h
@@ -8,20 +8,17 @@
  * Power Management Controller (PMC) - System peripherals registers.
  * Based on AT91RM9200 datasheet revision E.
  *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #ifndef AT91_PMC_H
 #define AT91_PMC_H
 
-#define        AT91_ASM_PMC_MOR        (AT91_PMC_BASE + 0x20)
-#define        AT91_ASM_PMC_PLLAR      (AT91_PMC_BASE + 0x28)
-#define        AT91_ASM_PMC_PLLBR      (AT91_PMC_BASE + 0x2c)
-#define AT91_ASM_PMC_MCKR      (AT91_PMC_BASE + 0x30)
-#define AT91_ASM_PMC_SR                (AT91_PMC_BASE + 0x68)
+#define        AT91_ASM_PMC_MOR        (ATMEL_BASE_PMC + 0x20)
+#define        AT91_ASM_PMC_PLLAR      (ATMEL_BASE_PMC + 0x28)
+#define        AT91_ASM_PMC_PLLBR      (ATMEL_BASE_PMC + 0x2c)
+#define AT91_ASM_PMC_MCKR      (ATMEL_BASE_PMC + 0x30)
+#define AT91_ASM_PMC_SR                (ATMEL_BASE_PMC + 0x68)
 
 #ifndef __ASSEMBLY__
 
@@ -35,13 +32,15 @@ typedef struct at91_pmc {
        u32     pcer;           /* 0x10 Peripheral Clock Enable Register */
        u32     pcdr;           /* 0x14 Peripheral Clock Disable Register */
        u32     pcsr;           /* 0x18 Peripheral Clock Status Register */
-       u32     reserved1;
+       u32     uckr;           /* 0x1C UTMI Clock Register */
        u32     mor;            /* 0x20 Main Oscilator Register */
        u32     mcfr;           /* 0x24 Main Clock Frequency Register */
        u32     pllar;          /* 0x28 PLL A Register */
        u32     pllbr;          /* 0x2C PLL B Register */
        u32     mckr;           /* 0x30 Master Clock Register */
-       u32     reserved2[3];
+       u32     reserved1;
+       u32     usb;            /* 0x38 USB Clock Register */
+       u32     reserved2;
        u32     pck[4];         /* 0x40 Programmable Clock Register 0 - 3 */
        u32     reserved3[4];
        u32     ier;            /* 0x60 Interrupt Enable Register */
@@ -53,7 +52,16 @@ typedef struct at91_pmc {
        u32     reserved5[21];
        u32     wpmr;           /* 0xE4 Write Protect Mode Register (CAP0) */
        u32     wpsr;           /* 0xE8 Write Protect Status Register (CAP0) */
+#ifdef CONFIG_SAMA5D3
+       u32     reserved6[8];
+       u32     pcer1;          /* 0x100 Periperial Clock Enable Register 1 */
+       u32     pcdr1;          /* 0x104 Periperial Clock Disable Register 1 */
+       u32     pcsr1;          /* 0x108 Periperial Clock Status Register 1 */
+       u32     pcr;            /* 0x10c Periperial Control Register */
+       u32     ocr;            /* 0x110 Oscillator Calibration Register */
+#else
        u32     reserved8[5];
+#endif
 } at91_pmc_t;
 
 #endif /* end not assembly */
@@ -80,6 +88,16 @@ typedef struct at91_pmc {
 #define AT91_PMC_MCKR_CSS_PLLB         0x00000003
 #define AT91_PMC_MCKR_CSS_MASK         0x00000003
 
+#ifdef CONFIG_SAMA5D3
+#define AT91_PMC_MCKR_PRES_1           0x00000000
+#define AT91_PMC_MCKR_PRES_2           0x00000010
+#define AT91_PMC_MCKR_PRES_4           0x00000020
+#define AT91_PMC_MCKR_PRES_8           0x00000030
+#define AT91_PMC_MCKR_PRES_16          0x00000040
+#define AT91_PMC_MCKR_PRES_32          0x00000050
+#define AT91_PMC_MCKR_PRES_64          0x00000060
+#define AT91_PMC_MCKR_PRES_MASK                0x00000070
+#else
 #define AT91_PMC_MCKR_PRES_1           0x00000000
 #define AT91_PMC_MCKR_PRES_2           0x00000004
 #define AT91_PMC_MCKR_PRES_4           0x00000008
@@ -88,11 +106,23 @@ typedef struct at91_pmc {
 #define AT91_PMC_MCKR_PRES_32          0x00000014
 #define AT91_PMC_MCKR_PRES_64          0x00000018
 #define AT91_PMC_MCKR_PRES_MASK                0x0000001C
+#endif
 
+#ifdef CONFIG_AT91RM9200
 #define AT91_PMC_MCKR_MDIV_1           0x00000000
 #define AT91_PMC_MCKR_MDIV_2           0x00000100
+#define AT91_PMC_MCKR_MDIV_3           0x00000200
+#define AT91_PMC_MCKR_MDIV_4           0x00000300
+#define AT91_PMC_MCKR_MDIV_MASK                0x00000300
+#else
+#define AT91_PMC_MCKR_MDIV_1           0x00000000
+#define AT91_PMC_MCKR_MDIV_2           0x00000100
+#ifdef CONFIG_SAMA5D3
+#define AT91_PMC_MCKR_MDIV_3           0x00000300
+#endif
 #define AT91_PMC_MCKR_MDIV_4           0x00000200
 #define AT91_PMC_MCKR_MDIV_MASK                0x00000300
+#endif
 
 #define AT91_PMC_MCKR_PLLADIV_1                0x00001000
 #define AT91_PMC_MCKR_PLLADIV_2                0x00002000
@@ -198,6 +228,14 @@ typedef struct at91_pmc {
 #define                        AT91_PMC_PDIV_1                 (0 << 12)
 #define                        AT91_PMC_PDIV_2                 (1 << 12)
 
+#ifdef CONFIG_AT91_LEGACY
+#define                AT91_PMC_USB                    (AT91_PMC + 0x38)       /* USB Clock Register */
+#endif
+#define                AT91_PMC_USBS_USB_PLLA          (0x0)           /* USB Clock Input is PLLA */
+#define                AT91_PMC_USBS_USB_UPLL          (0x1)           /* USB Clock Input is UPLL */
+#define                AT91_PMC_USBDIV_8               (0x7 <<  8)     /* USB Clock divided by 8 */
+#define                AT91_PMC_USBDIV_10              (0x9 <<  8)     /* USB Clock divided by 10 */
+
 #ifdef CONFIG_AT91_LEGACY
 #define        AT91_PMC_PCKR(n)        (AT91_PMC + 0x40 + ((n) * 4))   /* Programmable Clock 0-3 Registers */