Merge branch 'master' of git://www.denx.de/git/u-boot-imx

[u-boot] / arch / arm / include / asm / arch-at91 / at91sam9_sdramc.h

diff --git a/arch/arm/include/asm/arch-at91/at91sam9_sdramc.h b/arch/arm/include/asm/arch-at91/at91sam9_sdramc.h
index 2d4c49e04bb547dbceaa6796e6f4ca707782618d..3a076c6b80644a437962fd14d633e0f9ebef7130 100644 (file)
--- a/arch/arm/include/asm/arch-at91/at91sam9_sdramc.h
+++ b/arch/arm/include/asm/arch-at91/at91sam9_sdramc.h
@@ -8,10 +8,7 @@
  * SDRAM Controllers (SDRAMC) - System peripherals registers.
  * Based on AT91SAM9261 datasheet revision D.
  *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #ifndef AT91SAM9_SDRAMC_H
@@ -28,6 +25,21 @@
 #define AT91_ASM_SDRAMC_CR     (ATMEL_BASE_SDRAMC + 0x08)
 #define AT91_ASM_SDRAMC_MDR    (ATMEL_BASE_SDRAMC + 0x24)
 
+#else
+struct sdramc_reg {
+       u32     mr;
+       u32     tr;
+       u32     cr;
+       u32     lpr;
+       u32     ier;
+       u32     idr;
+       u32     imr;
+       u32     isr;
+       u32     mdr;
+};
+
+int sdramc_initialize(unsigned int sdram_address,
+                     const struct sdramc_reg *p);
 #endif
 
 /* SDRAM Controller (SDRAMC) registers */
@@ -65,11 +77,17 @@
 #define                        AT91_SDRAMC_DBW_32      (0 << 7)
 #define                        AT91_SDRAMC_DBW_16      (1 << 7)
 #define                AT91_SDRAMC_TWR         (0xf <<  8)             /* Write Recovery Delay */
+#define                AT91_SDRAMC_TWR_VAL(x)  (x << 8)
 #define                AT91_SDRAMC_TRC         (0xf << 12)             /* Row Cycle Delay */
+#define                        AT91_SDRAMC_TRC_VAL(x)  (x << 12)
 #define                AT91_SDRAMC_TRP         (0xf << 16)             /* Row Precharge Delay */
+#define                AT91_SDRAMC_TRP_VAL(x)  (x << 16)
 #define                AT91_SDRAMC_TRCD        (0xf << 20)             /* Row to Column Delay */
+#define                        AT91_SDRAMC_TRCD_VAL(x) (x << 20)
 #define                AT91_SDRAMC_TRAS        (0xf << 24)             /* Active to Precharge Delay */
+#define                AT91_SDRAMC_TRAS_VAL(x) (x << 24)
 #define                AT91_SDRAMC_TXSR        (0xf << 28)             /* Exit Self Refresh to Active Delay */
+#define                AT91_SDRAMC_TXSR_VAL(x) (x << 28)
 
 #define AT91_SDRAMC_LPR                (ATMEL_BASE_SDRAMC + 0x10)      /* SDRAM Controller Low Power Register */
 #define                AT91_SDRAMC_LPCB                (3 << 0)        /* Low-power Configurations */
@@ -96,5 +114,4 @@
 #define                        AT91_SDRAMC_MD_SDRAM            0
 #define                        AT91_SDRAMC_MD_LOW_POWER_SDRAM  1
 
-
 #endif