#define ESUB_CLK_BASE_ADDR 0x38000000
#define ESW_CONTRL_BASE_ADDR 0x38200000
#define GPIO2_BASE_ADDR 0x35003000
+#define HSOTG_BASE_ADDR 0x3f120000
+#define HSOTG_CTRL_BASE_ADDR 0x3f130000
#define KONA_MST_CLK_BASE_ADDR 0x3f001000
#define KONA_SLV_CLK_BASE_ADDR 0x3e011000
#define PMU_BSC_BASE_ADDR 0x3500d000
#define SECWD2_BASE_ADDR 0x35002f40
#define TIMER_BASE_ADDR 0x3e00d000
+#define HSOTG_DCTL_OFFSET 0x00000804
+#define HSOTG_DCTL_SFTDISCON_MASK 0x00000002
+
+#define HSOTG_CTRL_PHY_P1CTL_OFFSET 0x00000008
+#define HSOTG_CTRL_PHY_P1CTL_SOFT_RESET_MASK 0x00000002
+#define HSOTG_CTRL_PHY_P1CTL_NON_DRIVING_MASK 0x00000001
+
#endif