arm, davinci: Change byte order of RTC kick register values

[u-boot] / arch / arm / include / asm / arch-davinci / hardware.h

diff --git a/arch/arm/include/asm/arch-davinci/hardware.h b/arch/arm/include/asm/arch-davinci/hardware.h
index bea14993e6aa84f6991a47a21de3efd2944e248b..1c71540e481fb249879ab0d1c455e673d17cb9d3 100644 (file)
--- a/arch/arm/include/asm/arch-davinci/hardware.h
+++ b/arch/arm/include/asm/arch-davinci/hardware.h
@@ -230,6 +230,9 @@ typedef volatile unsigned int *     dv_reg_p;
 #define DAVINCI_LPSC_CFG5              38
 #define DAVINCI_LPSC_GEM               39
 #define DAVINCI_LPSC_IMCOP             40
+#define DAVINCI_LPSC_VPSSMASTER                47
+#define DAVINCI_LPSC_MJCP              50
+#define DAVINCI_LPSC_HDVICP            51
 
 #define DAVINCI_DM646X_LPSC_EMAC       14
 #define DAVINCI_DM646X_LPSC_UART0      26
@@ -385,6 +388,20 @@ struct davinci_psc_regs {
 #define PINMUX3                                0x01c4000c
 #define PINMUX4                                0x01c40010
 
+struct davinci_uart_ctrl_regs {
+       dv_reg  revid1;
+       dv_reg  res;
+       dv_reg  pwremu_mgmt;
+       dv_reg  mdr;
+};
+
+#define DAVINCI_UART_CTRL_BASE 0x28
+
+/* UART PWREMU_MGMT definitions */
+#define DAVINCI_UART_PWREMU_MGMT_FREE  (1 << 0)
+#define DAVINCI_UART_PWREMU_MGMT_URRST (1 << 13)
+#define DAVINCI_UART_PWREMU_MGMT_UTRST (1 << 14)
+
 #else /* CONFIG_SOC_DA8XX */
 
 struct davinci_pllc_regs {
@@ -431,6 +448,7 @@ struct davinci_pllc_regs {
 enum davinci_clk_ids {
        DAVINCI_SPI0_CLKID = 2,
        DAVINCI_UART2_CLKID = 2,
+       DAVINCI_MMC_CLKID = 2,
        DAVINCI_MDIO_CLKID = 4,
        DAVINCI_ARM_CLKID = 6,
        DAVINCI_PLLM_CLKID = 0xff,
@@ -462,12 +480,15 @@ struct davinci_syscfg_regs {
 #define davinci_syscfg_regs \
        ((struct davinci_syscfg_regs *)DAVINCI_BOOTCFG_BASE)
 
+#define pinmux(x)      (&davinci_syscfg_regs->pinmux[x])
+
 /* Emulation suspend bits */
 #define DAVINCI_SYSCFG_SUSPSRC_EMAC            (1 << 5)
 #define DAVINCI_SYSCFG_SUSPSRC_I2C             (1 << 16)
 #define DAVINCI_SYSCFG_SUSPSRC_SPI0            (1 << 21)
 #define DAVINCI_SYSCFG_SUSPSRC_SPI1            (1 << 22)
 #define DAVINCI_SYSCFG_SUSPSRC_UART0           (1 << 18)
+#define DAVINCI_SYSCFG_SUSPSRC_UART2           (1 << 20)
 #define DAVINCI_SYSCFG_SUSPSRC_TIMER0          (1 << 27)
 
 struct davinci_syscfg1_regs {
@@ -491,6 +512,9 @@ struct davinci_syscfg1_regs {
 #define VTP_READY              (1 << 15)
 #define VTP_IOPWRDWN           (1 << 14)
 
+#define DV_SYSCFG_KICK0_UNLOCK 0x83e70b13
+#define DV_SYSCFG_KICK1_UNLOCK 0x95a4f1e0
+
 /* Interrupt controller */
 struct davinci_aintc_regs {
        dv_reg  revid;
@@ -564,4 +588,43 @@ static inline int get_async3_src(void)
 #include <asm/arch/syscfg_defs.h>
 #include <asm/arch/timer_defs.h>
 #endif
+
+struct davinci_rtc {
+       dv_reg  second;
+       dv_reg  minutes;
+       dv_reg  hours;
+       dv_reg  day;
+       dv_reg  month; /* 0x10 */
+       dv_reg  year;
+       dv_reg  dotw;
+       dv_reg  resv1;
+       dv_reg  alarmsecond; /* 0x20 */
+       dv_reg  alarmminute;
+       dv_reg  alarmhour;
+       dv_reg  alarmday;
+       dv_reg  alarmmonth; /* 0x30 */
+       dv_reg  alarmyear;
+       dv_reg  resv2[2];
+       dv_reg  ctrl; /* 0x40 */
+       dv_reg  status;
+       dv_reg  irq;
+       dv_reg  complsb;
+       dv_reg  compmsb; /* 0x50 */
+       dv_reg  osc;
+       dv_reg  resv3[2];
+       dv_reg  scratch0; /* 0x60 */
+       dv_reg  scratch1;
+       dv_reg  scratch2;
+       dv_reg  kick0r;
+       dv_reg  kick1r; /* 0x70 */
+};
+
+#define RTC_STATE_BUSY 0x01
+#define RTC_STATE_RUN  0x02
+
+#define RTC_KICK0R_WE  0x83e70b13
+#define RTC_KICK1R_WE  0x95a4f1e0
+
+#define davinci_rtc_base ((struct davinci_rtc *)DAVINCI_RTC_BASE)
+
 #endif /* __ASM_ARCH_HARDWARE_H */