da8xx: add support for multiple PLL controllers

[u-boot] / arch / arm / include / asm / arch-davinci / hardware.h

diff --git a/arch/arm/include/asm/arch-davinci/hardware.h b/arch/arm/include/asm/arch-davinci/hardware.h
index b95fa97bacc154fe1e0be03287a93e5713e16070..646e2ced82709d6fdfc4ceae36788fbbaa53d638 100644 (file)
--- a/arch/arm/include/asm/arch-davinci/hardware.h
+++ b/arch/arm/include/asm/arch-davinci/hardware.h
@@ -129,6 +129,7 @@ typedef volatile unsigned int *     dv_reg_p;
 #define DAVINCI_TIMER1_BASE                    0x01c21000
 #define DAVINCI_WDOG_BASE                      0x01c21000
 #define DAVINCI_PLL_CNTRL0_BASE                        0x01c11000
+#define DAVINCI_PLL_CNTRL1_BASE                        0x01e1a000
 #define DAVINCI_PSC0_BASE                      0x01c10000
 #define DAVINCI_PSC1_BASE                      0x01e27000
 #define DAVINCI_SPI0_BASE                      0x01c41000
@@ -140,6 +141,8 @@ typedef volatile unsigned int *     dv_reg_p;
 #define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE   0x01e22000
 #define DAVINCI_EMAC_WRAPPER_RAM_BASE          0x01e20000
 #define DAVINCI_MDIO_CNTRL_REGS_BASE           0x01e24000
+#define DAVINCI_MMC_SD0_BASE                   0x01c40000
+#define DAVINCI_MMC_SD1_BASE                   0x01e1b000
 #define DAVINCI_ASYNC_EMIF_CNTRL_BASE          0x68000000
 #define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE       0x40000000
 #define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE       0x60000000
@@ -209,50 +212,69 @@ typedef volatile unsigned int *   dv_reg_p;
 #define DAVINCI_DM646X_LPSC_EMAC       14
 #define DAVINCI_DM646X_LPSC_UART0      26
 #define DAVINCI_DM646X_LPSC_I2C                31
+#define DAVINCI_DM646X_LPSC_TIMER0     34
 
 #else /* CONFIG_SOC_DA8XX */
 
-enum davinci_lpsc_ids {
-       DAVINCI_LPSC_TPCC = 0,
-       DAVINCI_LPSC_TPTC0,
-       DAVINCI_LPSC_TPTC1,
-       DAVINCI_LPSC_AEMIF,
-       DAVINCI_LPSC_SPI0,
-       DAVINCI_LPSC_MMC_SD,
-       DAVINCI_LPSC_AINTC,
-       DAVINCI_LPSC_ARM_RAM_ROM,
-       DAVINCI_LPSC_SECCTL_KEYMGR,
-       DAVINCI_LPSC_UART0,
-       DAVINCI_LPSC_SCR0,
-       DAVINCI_LPSC_SCR1,
-       DAVINCI_LPSC_SCR2,
-       DAVINCI_LPSC_DMAX,
-       DAVINCI_LPSC_ARM,
-       DAVINCI_LPSC_GEM,
-       /* for LPSCs in PSC1, offset from 32 for differentiation */
-       DAVINCI_LPSC_PSC1_BASE = 32,
-       DAVINCI_LPSC_USB11,
-       DAVINCI_LPSC_USB20,
-       DAVINCI_LPSC_GPIO,
-       DAVINCI_LPSC_UHPI,
-       DAVINCI_LPSC_EMAC,
-       DAVINCI_LPSC_DDR_EMIF,
-       DAVINCI_LPSC_McASP0,
-       DAVINCI_LPSC_McASP1,
-       DAVINCI_LPSC_McASP2,
-       DAVINCI_LPSC_SPI1,
-       DAVINCI_LPSC_I2C1,
-       DAVINCI_LPSC_UART1,
-       DAVINCI_LPSC_UART2,
-       DAVINCI_LPSC_LCDC,
-       DAVINCI_LPSC_ePWM,
-       DAVINCI_LPSC_eCAP,
-       DAVINCI_LPSC_eQEP,
-       DAVINCI_LPSC_SCR_P0,
-       DAVINCI_LPSC_SCR_P1,
-       DAVINCI_LPSC_CR_P3,
-       DAVINCI_LPSC_L3_CBA_RAM
-};
+#define DAVINCI_LPSC_TPCC              0
+#define DAVINCI_LPSC_TPTC0             1
+#define DAVINCI_LPSC_TPTC1             2
+#define DAVINCI_LPSC_AEMIF             3
+#define DAVINCI_LPSC_SPI0              4
+#define DAVINCI_LPSC_MMC_SD            5
+#define DAVINCI_LPSC_AINTC             6
+#define DAVINCI_LPSC_ARM_RAM_ROM       7
+#define DAVINCI_LPSC_SECCTL_KEYMGR     8
+#define DAVINCI_LPSC_UART0             9
+#define DAVINCI_LPSC_SCR0              10
+#define DAVINCI_LPSC_SCR1              11
+#define DAVINCI_LPSC_SCR2              12
+#define DAVINCI_LPSC_DMAX              13
+#define DAVINCI_LPSC_ARM               14
+#define DAVINCI_LPSC_GEM               15
+
+/* for LPSCs in PSC1, offset from 32 for differentiation */
+#define DAVINCI_LPSC_PSC1_BASE         32
+#define DAVINCI_LPSC_USB20             (DAVINCI_LPSC_PSC1_BASE + 1)
+#define DAVINCI_LPSC_USB11             (DAVINCI_LPSC_PSC1_BASE + 2)
+#define DAVINCI_LPSC_GPIO              (DAVINCI_LPSC_PSC1_BASE + 3)
+#define DAVINCI_LPSC_UHPI              (DAVINCI_LPSC_PSC1_BASE + 4)
+#define DAVINCI_LPSC_EMAC              (DAVINCI_LPSC_PSC1_BASE + 5)
+#define DAVINCI_LPSC_DDR_EMIF          (DAVINCI_LPSC_PSC1_BASE + 6)
+#define DAVINCI_LPSC_McASP0            (DAVINCI_LPSC_PSC1_BASE + 7)
+#define DAVINCI_LPSC_SPI1              (DAVINCI_LPSC_PSC1_BASE + 10)
+#define DAVINCI_LPSC_I2C1              (DAVINCI_LPSC_PSC1_BASE + 11)
+#define DAVINCI_LPSC_UART1             (DAVINCI_LPSC_PSC1_BASE + 12)
+#define DAVINCI_LPSC_UART2             (DAVINCI_LPSC_PSC1_BASE + 13)
+#define DAVINCI_LPSC_LCDC              (DAVINCI_LPSC_PSC1_BASE + 16)
+#define DAVINCI_LPSC_ePWM              (DAVINCI_LPSC_PSC1_BASE + 17)
+#define DAVINCI_LPSC_eCAP              (DAVINCI_LPSC_PSC1_BASE + 20)
+#define DAVINCI_LPSC_L3_CBA_RAM                (DAVINCI_LPSC_PSC1_BASE + 31)
+
+/* DA830-specific peripherals */
+#define DAVINCI_LPSC_McASP1            (DAVINCI_LPSC_PSC1_BASE + 8)
+#define DAVINCI_LPSC_McASP2            (DAVINCI_LPSC_PSC1_BASE + 9)
+#define DAVINCI_LPSC_eQEP              (DAVINCI_LPSC_PSC1_BASE + 21)
+#define DAVINCI_LPSC_SCR8              (DAVINCI_LPSC_PSC1_BASE + 24)
+#define DAVINCI_LPSC_SCR7              (DAVINCI_LPSC_PSC1_BASE + 25)
+#define DAVINCI_LPSC_SCR12             (DAVINCI_LPSC_PSC1_BASE + 26)
+
+/* DA850-specific peripherals */
+#define DAVINCI_LPSC_TPCC1             (DAVINCI_LPSC_PSC1_BASE + 0)
+#define DAVINCI_LPSC_SATA              (DAVINCI_LPSC_PSC1_BASE + 8)
+#define DAVINCI_LPSC_VPIF              (DAVINCI_LPSC_PSC1_BASE + 9)
+#define DAVINCI_LPSC_McBSP0            (DAVINCI_LPSC_PSC1_BASE + 14)
+#define DAVINCI_LPSC_McBSP1            (DAVINCI_LPSC_PSC1_BASE + 15)
+#define DAVINCI_LPSC_MMC_SD1           (DAVINCI_LPSC_PSC1_BASE + 18)
+#define DAVINCI_LPSC_uPP               (DAVINCI_LPSC_PSC1_BASE + 19)
+#define DAVINCI_LPSC_TPTC2             (DAVINCI_LPSC_PSC1_BASE + 21)
+#define DAVINCI_LPSC_SCR_F0            (DAVINCI_LPSC_PSC1_BASE + 24)
+#define DAVINCI_LPSC_SCR_F1            (DAVINCI_LPSC_PSC1_BASE + 25)
+#define DAVINCI_LPSC_SCR_F2            (DAVINCI_LPSC_PSC1_BASE + 26)
+#define DAVINCI_LPSC_SCR_F6            (DAVINCI_LPSC_PSC1_BASE + 27)
+#define DAVINCI_LPSC_SCR_F7            (DAVINCI_LPSC_PSC1_BASE + 28)
+#define DAVINCI_LPSC_SCR_F8            (DAVINCI_LPSC_PSC1_BASE + 29)
+#define DAVINCI_LPSC_BR_F7             (DAVINCI_LPSC_PSC1_BASE + 30)
 
 #endif /* CONFIG_SOC_DA8XX */
 
@@ -366,7 +388,8 @@ struct davinci_pllc_regs {
        dv_reg  emucnt1;
 };
 
-#define davinci_pllc_regs ((struct davinci_pllc_regs *)DAVINCI_PLL_CNTRL0_BASE)
+#define davinci_pllc0_regs ((struct davinci_pllc_regs *)DAVINCI_PLL_CNTRL0_BASE)
+#define davinci_pllc1_regs ((struct davinci_pllc_regs *)DAVINCI_PLL_CNTRL1_BASE)
 #define DAVINCI_PLLC_DIV_MASK  0x1f
 
 #define ASYNC3          get_async3_src()