Davinci: ea20: set console on UART0

[u-boot] / arch / arm / include / asm / arch-davinci / hardware.h

diff --git a/arch/arm/include/asm/arch-davinci/hardware.h b/arch/arm/include/asm/arch-davinci/hardware.h
index f537c4b1a9720eac66a396693ef4e77fd9105560..946c793ab5773a9b9a0b408062ee45e31b7521e5 100644 (file)
--- a/arch/arm/include/asm/arch-davinci/hardware.h
+++ b/arch/arm/include/asm/arch-davinci/hardware.h
@@ -56,6 +56,7 @@ typedef volatile unsigned int *       dv_reg_p;
 #define DAVINCI_DMA_3PTC1_BASE                 (0x01c10400)
 #define DAVINCI_UART0_BASE                     (0x01c20000)
 #define DAVINCI_UART1_BASE                     (0x01c20400)
+#define DAVINCI_TIMER3_BASE                    (0x01c20800)
 #define DAVINCI_I2C_BASE                       (0x01c21000)
 #define DAVINCI_TIMER0_BASE                    (0x01c21400)
 #define DAVINCI_TIMER1_BASE                    (0x01c21800)
@@ -63,6 +64,7 @@ typedef volatile unsigned int *       dv_reg_p;
 #define DAVINCI_PWM0_BASE                      (0x01c22000)
 #define DAVINCI_PWM1_BASE                      (0x01c22400)
 #define DAVINCI_PWM2_BASE                      (0x01c22800)
+#define DAVINCI_TIMER4_BASE                    (0x01c23800)
 #define DAVINCI_SYSTEM_MODULE_BASE             (0x01c40000)
 #define DAVINCI_PLL_CNTRL0_BASE                        (0x01c40800)
 #define DAVINCI_PLL_CNTRL1_BASE                        (0x01c40c00)
@@ -108,6 +110,9 @@ typedef volatile unsigned int *     dv_reg_p;
 #define DAVINCI_MMC_SD1_BASE                   0x01d00000
 #define DAVINCI_ASYNC_EMIF_CNTRL_BASE          0x01d10000
 #define DAVINCI_MMC_SD0_BASE                   0x01d11000
+#define DAVINCI_DDR_EMIF_CTRL_BASE             0x20000000
+#define DAVINCI_SPI0_BASE                      0x01c66000
+#define DAVINCI_SPI1_BASE                      0x01c66800
 
 #elif defined(CONFIG_SOC_DM646X)
 #define DAVINCI_ASYNC_EMIF_CNTRL_BASE          0x20008000
@@ -128,7 +133,9 @@ typedef volatile unsigned int *     dv_reg_p;
 #define DAVINCI_TIMER0_BASE                    0x01c20000
 #define DAVINCI_TIMER1_BASE                    0x01c21000
 #define DAVINCI_WDOG_BASE                      0x01c21000
+#define DAVINCI_RTC_BASE                       0x01c23000
 #define DAVINCI_PLL_CNTRL0_BASE                        0x01c11000
+#define DAVINCI_PLL_CNTRL1_BASE                        0x01e1a000
 #define DAVINCI_PSC0_BASE                      0x01c10000
 #define DAVINCI_PSC1_BASE                      0x01e27000
 #define DAVINCI_SPI0_BASE                      0x01c41000
@@ -140,8 +147,11 @@ typedef volatile unsigned int *    dv_reg_p;
 #define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE   0x01e22000
 #define DAVINCI_EMAC_WRAPPER_RAM_BASE          0x01e20000
 #define DAVINCI_MDIO_CNTRL_REGS_BASE           0x01e24000
+#define DAVINCI_SYSCFG1_BASE                   0x01e2c000
 #define DAVINCI_MMC_SD0_BASE                   0x01c40000
 #define DAVINCI_MMC_SD1_BASE                   0x01e1b000
+#define DAVINCI_TIMER2_BASE                    0x01f0c000
+#define DAVINCI_TIMER3_BASE                    0x01f0d000
 #define DAVINCI_ASYNC_EMIF_CNTRL_BASE          0x68000000
 #define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE       0x40000000
 #define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE       0x60000000
@@ -152,8 +162,16 @@ typedef volatile unsigned int *    dv_reg_p;
 #define DAVINCI_DDR_EMIF_DATA_BASE             0xc0000000
 #define DAVINCI_INTC_BASE                      0xfffee000
 #define DAVINCI_BOOTCFG_BASE                   0x01c14000
+#define DAVINCI_L3CBARAM_BASE                  0x80000000
 #define JTAG_ID_REG                            (DAVINCI_BOOTCFG_BASE + 0x18)
-
+#define CHIP_REV_ID_REG                                (DAVINCI_BOOTCFG_BASE + 0x24)
+#define HOST1CFG                               (DAVINCI_BOOTCFG_BASE + 0x44)
+#define PSC0_MDCTL                             (DAVINCI_PSC0_BASE + 0xa00)
+
+#define GPIO_BANK0_REG_DIR_ADDR                        (DAVINCI_GPIO_BASE + 0x10)
+#define GPIO_BANK0_REG_OPDATA_ADDR             (DAVINCI_GPIO_BASE + 0x14)
+#define GPIO_BANK0_REG_SET_ADDR                        (DAVINCI_GPIO_BASE + 0x18)
+#define GPIO_BANK0_REG_CLR_ADDR                        (DAVINCI_GPIO_BASE + 0x1c)
 #define GPIO_BANK2_REG_DIR_ADDR                        (DAVINCI_GPIO_BASE + 0x38)
 #define GPIO_BANK2_REG_OPDATA_ADDR             (DAVINCI_GPIO_BASE + 0x3c)
 #define GPIO_BANK2_REG_SET_ADDR                        (DAVINCI_GPIO_BASE + 0x40)
@@ -247,6 +265,7 @@ typedef volatile unsigned int *     dv_reg_p;
 #define DAVINCI_LPSC_UART2             (DAVINCI_LPSC_PSC1_BASE + 13)
 #define DAVINCI_LPSC_LCDC              (DAVINCI_LPSC_PSC1_BASE + 16)
 #define DAVINCI_LPSC_ePWM              (DAVINCI_LPSC_PSC1_BASE + 17)
+#define DAVINCI_LPSC_MMCSD1            (DAVINCI_LPSC_PSC1_BASE + 18)
 #define DAVINCI_LPSC_eCAP              (DAVINCI_LPSC_PSC1_BASE + 20)
 #define DAVINCI_LPSC_L3_CBA_RAM                (DAVINCI_LPSC_PSC1_BASE + 31)
 
@@ -278,6 +297,7 @@ typedef volatile unsigned int *     dv_reg_p;
 #endif /* CONFIG_SOC_DA8XX */
 
 void lpsc_on(unsigned int id);
+void lpsc_syncreset(unsigned int id);
 void dsp_on(void);
 
 void davinci_enable_uart0(void);
@@ -309,6 +329,11 @@ void davinci_errata_workarounds(void);
 
 #else /* CONFIG_SOC_DA8XX */
 
+#define        PSC_ENABLE              0x3
+#define        PSC_DISABLE             0x2
+#define        PSC_SYNCRESET           0x1
+#define        PSC_SWRSTDISABLE        0x0
+
 #define PSC_PSC0_MODULE_ID_CNT         16
 #define PSC_PSC1_MODULE_ID_CNT         32
 
@@ -338,6 +363,9 @@ struct davinci_psc_regs {
 
 #endif /* CONFIG_SOC_DA8XX */
 
+#define PSC_MDSTAT_STATE               0x3f
+#define PSC_MDCTL_NEXT                 0x07
+
 #ifndef CONFIG_SOC_DA8XX
 
 /* Miscellania... */
@@ -387,7 +415,8 @@ struct davinci_pllc_regs {
        dv_reg  emucnt1;
 };
 
-#define davinci_pllc_regs ((struct davinci_pllc_regs *)DAVINCI_PLL_CNTRL0_BASE)
+#define davinci_pllc0_regs ((struct davinci_pllc_regs *)DAVINCI_PLL_CNTRL0_BASE)
+#define davinci_pllc1_regs ((struct davinci_pllc_regs *)DAVINCI_PLL_CNTRL1_BASE)
 #define DAVINCI_PLLC_DIV_MASK  0x1f
 
 #define ASYNC3          get_async3_src()
@@ -432,9 +461,30 @@ struct davinci_syscfg_regs {
 #define DAVINCI_SYSCFG_SUSPSRC_I2C             (1 << 16)
 #define DAVINCI_SYSCFG_SUSPSRC_SPI0            (1 << 21)
 #define DAVINCI_SYSCFG_SUSPSRC_SPI1            (1 << 22)
-#define DAVINCI_SYSCFG_SUSPSRC_UART2           (1 << 20)
+#define DAVINCI_SYSCFG_SUSPSRC_UART0           (1 << 18)
 #define DAVINCI_SYSCFG_SUSPSRC_TIMER0          (1 << 27)
 
+struct davinci_syscfg1_regs {
+       dv_reg  vtpio_ctl;
+       dv_reg  ddr_slew;
+       dv_reg  deepsleep;
+       dv_reg  pupd_ena;
+       dv_reg  pupd_sel;
+       dv_reg  rxactive;
+       dv_reg  pwrdwn;
+};
+
+#define davinci_syscfg1_regs \
+       ((struct davinci_syscfg1_regs *)DAVINCI_SYSCFG1_BASE)
+
+#define DDR_SLEW_CMOSEN_BIT    4
+
+#define VTP_POWERDWN           (1 << 6)
+#define VTP_LOCK               (1 << 7)
+#define VTP_CLKRZ              (1 << 13)
+#define VTP_READY              (1 << 15)
+#define VTP_IOPWRDWN           (1 << 14)
+
 /* Interrupt controller */
 struct davinci_aintc_regs {
        dv_reg  revid;
@@ -498,4 +548,14 @@ static inline int get_async3_src(void)
 
 #endif /* CONFIG_SOC_DA8XX */
 
+#if defined(CONFIG_SOC_DM365)
+#include <asm/arch/aintc_defs.h>
+#include <asm/arch/ddr2_defs.h>
+#include <asm/arch/emif_defs.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/pll_defs.h>
+#include <asm/arch/psc_defs.h>
+#include <asm/arch/syscfg_defs.h>
+#include <asm/arch/timer_defs.h>
+#endif
 #endif /* __ASM_ARCH_HARDWARE_H */