Merge git://git.denx.de/u-boot-mpc85xx

[u-boot] / arch / arm / include / asm / arch-fsl-layerscape / config.h

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index 6ee75cb4e83f5f2f552575ae535ccec370509f40..6c3ba494f891d9d0582484883412e0288c489bd5 100644 (file)
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -12,17 +12,6 @@
 
 #define CONFIG_STANDALONE_LOAD_ADDR    0x80300000
 
-#ifdef CONFIG_SYS_FSL_DDR4
-#define CONFIG_SYS_FSL_DDRC_GEN4
-#else
-#define CONFIG_SYS_FSL_DDRC_ARM_GEN3   /* Enable Freescale ARM DDR3 driver */
-#endif
-
-#ifndef CONFIG_ARCH_LS1012A
-#define CONFIG_SYS_FSL_DDR             /* Freescale DDR driver */
-#define CONFIG_SYS_FSL_DDR_VER         FSL_DDR_VER_5_0
-#endif
-
 /*
  * Reserve secure memory
  * To be aligned with MMU block size
@@ -32,19 +21,17 @@
 #ifdef CONFIG_LS2080A
 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS          { 1, 1, 4, 4 }
 #define        SRDS_MAX_LANES  8
-#define CONFIG_SYS_FSL_SRDS_1
-#define CONFIG_SYS_FSL_SRDS_2
 #define CONFIG_SYS_PAGE_SIZE           0x10000
 #ifndef L1_CACHE_BYTES
 #define L1_CACHE_SHIFT         6
 #define L1_CACHE_BYTES         BIT(L1_CACHE_SHIFT)
+#define CONFIG_FSL_TZASC_400
 #endif
 
 #define CONFIG_SYS_FSL_OCRAM_BASE      0x18000000      /* initial RAM */
 #define CONFIG_SYS_FSL_OCRAM_SIZE      0x00200000      /* 2M */
 
 /* DDR */
-#define CONFIG_SYS_FSL_DDR_LE
 #define CONFIG_SYS_LS2_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
 #define CONFIG_MAX_MEM_MAPPED          CONFIG_SYS_LS2_DDR_BLOCK1_SIZE
 
@@ -162,15 +149,12 @@
 #define CONFIG_SYS_FSL_PEX_LUT_BE
 #define CONFIG_SYS_FSL_SEC_BE
 
-#define CONFIG_SYS_FSL_SRDS_1
-
 /* SoC related */
 #ifdef CONFIG_LS1043A
 #define CONFIG_SYS_FMAN_V3
 #define CONFIG_SYS_NUM_FMAN                    1
 #define CONFIG_SYS_NUM_FM1_DTSEC               7
 #define CONFIG_SYS_NUM_FM1_10GEC               1
-#define CONFIG_SYS_FSL_DDR_BE
 #define CONFIG_SYS_DDR_BLOCK1_SIZE             ((phys_size_t)2 << 30)
 #define CONFIG_MAX_MEM_MAPPED                  CONFIG_SYS_DDR_BLOCK1_SIZE
 
@@ -208,11 +192,9 @@
 #define CONFIG_SYS_NUM_FMAN                    1
 #define CONFIG_SYS_NUM_FM1_DTSEC               8
 #define CONFIG_SYS_NUM_FM1_10GEC               2
-#define CONFIG_SYS_FSL_DDR_BE
 #define CONFIG_SYS_DDR_BLOCK1_SIZE  ((phys_size_t)2 << 30)
 #define CONFIG_MAX_MEM_MAPPED           CONFIG_SYS_DDR_BLOCK1_SIZE
 
-#define CONFIG_SYS_FSL_SRDS_2
 #define CONFIG_SYS_FSL_IFC_BE
 #define CONFIG_SYS_FSL_SFP_VER_3_2
 #define CONFIG_SYS_FSL_SNVS_LE