Merge git://git.denx.de/u-boot-mpc85xx

[u-boot] / arch / arm / include / asm / arch-fsl-layerscape / config.h

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index b0ad4b462689f6e48ab89d6f2ad3cb2069244002..6c3ba494f891d9d0582484883412e0288c489bd5 100644 (file)
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -7,18 +7,10 @@
 #ifndef _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_
 #define _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_
 
+#include <linux/kconfig.h>
 #include <fsl_ddrc_version.h>
 
-#ifdef CONFIG_SYS_FSL_DDR4
-#define CONFIG_SYS_FSL_DDRC_GEN4
-#else
-#define CONFIG_SYS_FSL_DDRC_ARM_GEN3   /* Enable Freescale ARM DDR3 driver */
-#endif
-
-#ifndef CONFIG_LS1012A
-#define CONFIG_SYS_FSL_DDR             /* Freescale DDR driver */
-#define CONFIG_SYS_FSL_DDR_VER         FSL_DDR_VER_5_0
-#endif
+#define CONFIG_STANDALONE_LOAD_ADDR    0x80300000
 
 /*
  * Reserve secure memory
@@ -27,26 +19,19 @@
 #define CONFIG_SYS_MEM_RESERVE_SECURE  (2048 * 1024)   /* 2MB */
 
 #ifdef CONFIG_LS2080A
-#define CONFIG_MAX_CPUS                                16
-#define CONFIG_SYS_FSL_IFC_BANK_COUNT          8
-#define CONFIG_NUM_DDR_CONTROLLERS             3
-#define CONFIG_SYS_FSL_HAS_DP_DDR              /* Runtime check to confirm */
 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS          { 1, 1, 4, 4 }
 #define        SRDS_MAX_LANES  8
-#define CONFIG_SYS_FSL_SRDS_1
-#define CONFIG_SYS_FSL_SRDS_2
 #define CONFIG_SYS_PAGE_SIZE           0x10000
-#define CONFIG_SYS_CACHELINE_SIZE      64
 #ifndef L1_CACHE_BYTES
 #define L1_CACHE_SHIFT         6
 #define L1_CACHE_BYTES         BIT(L1_CACHE_SHIFT)
+#define CONFIG_FSL_TZASC_400
 #endif
 
 #define CONFIG_SYS_FSL_OCRAM_BASE      0x18000000      /* initial RAM */
 #define CONFIG_SYS_FSL_OCRAM_SIZE      0x00200000      /* 2M */
 
 /* DDR */
-#define CONFIG_SYS_FSL_DDR_LE
 #define CONFIG_SYS_LS2_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
 #define CONFIG_MAX_MEM_MAPPED          CONFIG_SYS_LS2_DDR_BLOCK1_SIZE
 
@@ -150,8 +135,6 @@
 
 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC          1
 #elif defined(CONFIG_FSL_LSCH2)
-#define CONFIG_SYS_CACHELINE_SIZE              64
-#define CONFIG_NUM_DDR_CONTROLLERS             1
 #define CONFIG_SYS_FSL_SEC_COMPAT              5
 #define CONFIG_SYS_FSL_OCRAM_BASE              0x10000000 /* initial RAM */
 #define CONFIG_SYS_FSL_OCRAM_SIZE              0x00200000 /* 2M */
@@ -166,16 +149,12 @@
 #define CONFIG_SYS_FSL_PEX_LUT_BE
 #define CONFIG_SYS_FSL_SEC_BE
 
-#define CONFIG_SYS_FSL_SRDS_1
 /* SoC related */
 #ifdef CONFIG_LS1043A
-#define CONFIG_MAX_CPUS                                4
 #define CONFIG_SYS_FMAN_V3
 #define CONFIG_SYS_NUM_FMAN                    1
 #define CONFIG_SYS_NUM_FM1_DTSEC               7
 #define CONFIG_SYS_NUM_FM1_10GEC               1
-#define CONFIG_SYS_FSL_IFC_BANK_COUNT          4
-#define CONFIG_SYS_FSL_DDR_BE
 #define CONFIG_SYS_DDR_BLOCK1_SIZE             ((phys_size_t)2 << 30)
 #define CONFIG_MAX_MEM_MAPPED                  CONFIG_SYS_DDR_BLOCK1_SIZE
 
@@ -203,24 +182,19 @@
 #define CONFIG_SYS_FSL_ERRATUM_A009942
 #define CONFIG_SYS_FSL_ERRATUM_A009660
 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC          1
-#elif defined(CONFIG_LS1012A)
-#define CONFIG_MAX_CPUS                         1
+#elif defined(CONFIG_ARCH_LS1012A)
 #undef CONFIG_SYS_FSL_DDRC_ARM_GEN3
 
 #define GICD_BASE              0x01401000
 #define GICC_BASE              0x01402000
-#elif defined(CONFIG_LS1046A)
-#define CONFIG_MAX_CPUS                                4
+#elif defined(CONFIG_ARCH_LS1046A)
 #define CONFIG_SYS_FMAN_V3
 #define CONFIG_SYS_NUM_FMAN                    1
 #define CONFIG_SYS_NUM_FM1_DTSEC               8
 #define CONFIG_SYS_NUM_FM1_10GEC               2
-#define CONFIG_SYS_FSL_IFC_BANK_COUNT          4
-#define CONFIG_SYS_FSL_DDR_BE
 #define CONFIG_SYS_DDR_BLOCK1_SIZE  ((phys_size_t)2 << 30)
 #define CONFIG_MAX_MEM_MAPPED           CONFIG_SYS_DDR_BLOCK1_SIZE
 
-#define CONFIG_SYS_FSL_SRDS_2
 #define CONFIG_SYS_FSL_IFC_BE
 #define CONFIG_SYS_FSL_SFP_VER_3_2
 #define CONFIG_SYS_FSL_SNVS_LE
@@ -236,6 +210,12 @@
 #define GICC_BASE              0x01420000
 
 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC          1
+
+#define CONFIG_SYS_FSL_ERRATUM_A008511
+#define CONFIG_SYS_FSL_ERRATUM_A009801
+#define CONFIG_SYS_FSL_ERRATUM_A009803
+#define CONFIG_SYS_FSL_ERRATUM_A009942
+#define CONFIG_SYS_FSL_ERRATUM_A010165
 #else
 #error SoC not defined
 #endif