armv8: LS2080A: Rename LS2085A to reflect LS2080A

[u-boot] / arch / arm / include / asm / arch-fsl-layerscape / config.h

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index dd7203f36eb9ba4f7a738eccfc9cd2909a6f57a9..f79a0e8ba39902e7ef38b3fcf8b8872a866446f0 100644 (file)
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -17,10 +17,10 @@
 #define CONFIG_SYS_FSL_DDR             /* Freescale DDR driver */
 #define CONFIG_SYS_FSL_DDR_VER         FSL_DDR_VER_5_0
 
-#if defined(CONFIG_LS2085A)
+#if defined(CONFIG_LS2080A)
 #define CONFIG_MAX_CPUS                                16
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT          8
-#define CONFIG_NUM_DDR_CONTROLLERS             3
+#define CONFIG_NUM_DDR_CONTROLLERS             2
 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS          { 1, 1, 4, 4 }
 #define        SRDS_MAX_LANES  8
 #define CONFIG_SYS_FSL_SRDS_1
@@ -89,6 +89,53 @@
 #define CONFIG_SYS_FSL_ERRATUM_A008514
 #define CONFIG_SYS_FSL_ERRATUM_A008585
 #define CONFIG_SYS_FSL_ERRATUM_A008751
+#elif defined(CONFIG_LS1043A)
+#define CONFIG_MAX_CPUS                                4
+#define CONFIG_SYS_CACHELINE_SIZE              64
+#define CONFIG_SYS_FMAN_V3
+#define CONFIG_SYS_NUM_FMAN                    1
+#define CONFIG_SYS_NUM_FM1_DTSEC               7
+#define CONFIG_SYS_NUM_FM1_10GEC               1
+#define CONFIG_SYS_FSL_IFC_BANK_COUNT          4
+#define CONFIG_NUM_DDR_CONTROLLERS             1
+#define CONFIG_SYS_CCSRBAR_DEFAULT             0x01000000
+#define CONFIG_SYS_FSL_SEC_COMPAT              5
+#define CONFIG_SYS_FSL_OCRAM_BASE              0x10000000 /* initial RAM */
+#define CONFIG_SYS_FSL_OCRAM_SIZE              0x200000 /* 2 MiB */
+#define CONFIG_SYS_FSL_DDR_BE
+#define CONFIG_SYS_LS1_DDR_BLOCK1_SIZE  ((phys_size_t)2 << 30)
+#define CONFIG_MAX_MEM_MAPPED           CONFIG_SYS_LS1_DDR_BLOCK1_SIZE
+
+#define CONFIG_SYS_FSL_CCSR_GUR_BE
+#define CONFIG_SYS_FSL_CCSR_SCFG_BE
+#define CONFIG_SYS_FSL_IFC_BE
+#define CONFIG_SYS_FSL_ESDHC_BE
+#define CONFIG_SYS_FSL_WDOG_BE
+#define CONFIG_SYS_FSL_DSPI_BE
+#define CONFIG_SYS_FSL_QSPI_BE
+
+#define QE_MURAM_SIZE          0x6000UL
+#define MAX_QE_RISC            1
+#define QE_NUM_OF_SNUM         28
+
+#define SRDS_MAX_LANES         4
+#define CONFIG_SYS_FSL_SRDS_1
+#define CONFIG_SYS_FSL_PCIE_COMPAT             "fsl,qoriq-pcie-v2.4"
+
+#define CONFIG_SYS_FSL_SFP_VER_3_2
+#define CONFIG_SYS_FSL_SNVS_LE
+#define CONFIG_SYS_FSL_SEC_LE
+#define CONFIG_SYS_FSL_SFP_BE
+#define CONFIG_SYS_FSL_SRK_LE
+#define CONFIG_KEY_REVOCATION
+
+/* SMMU Defintions */
+#define SMMU_BASE              0x09000000
+
+/* Generic Interrupt Controller Definitions */
+#define GICD_BASE              0x01401000
+#define GICC_BASE              0x01402000
+
 #else
 #error SoC not defined
 #endif