arm64: Remove non-full-va map code

[u-boot] / arch / arm / include / asm / arch-fsl-layerscape / cpu.h

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
index 15ade84c48ae6da4b71b4b88d6638f20f2466e79..93bbda3324860b2ccad062936d558217934c0f67 100644 (file)
--- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
@@ -117,48 +117,48 @@ static const struct sys_mmu_table early_mmu_table[] = {
 #ifdef CONFIG_FSL_LSCH3
        { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
          CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE,
-         PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
+         PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
        { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
-         CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE },
+         CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PTE_BLOCK_NON_SHARE },
        /* For IFC Region #1, only the first 4MB is cache-enabled */
        { CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_BASE1,
-         CONFIG_SYS_FSL_IFC_SIZE1_1, MT_NORMAL, PMD_SECT_NON_SHARE },
+         CONFIG_SYS_FSL_IFC_SIZE1_1, MT_NORMAL, PTE_BLOCK_NON_SHARE },
        { CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
          CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
          CONFIG_SYS_FSL_IFC_SIZE1 - CONFIG_SYS_FSL_IFC_SIZE1_1,
-         MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+         MT_DEVICE_NGNRNE, PTE_BLOCK_NON_SHARE },
        { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FSL_IFC_BASE1,
-         CONFIG_SYS_FSL_IFC_SIZE1, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+         CONFIG_SYS_FSL_IFC_SIZE1, MT_DEVICE_NGNRNE, PTE_BLOCK_NON_SHARE },
        { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
          CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL,
-         PMD_SECT_OUTER_SHARE | PMD_SECT_NS },
+         PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS },
        /* Map IFC region #2 up to CONFIG_SYS_FLASH_BASE for NAND boot */
        { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
          CONFIG_SYS_FLASH_BASE - CONFIG_SYS_FSL_IFC_BASE2,
-         MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+         MT_DEVICE_NGNRNE, PTE_BLOCK_NON_SHARE },
        { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
          CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE,
-         PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
+         PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
        { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
          CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL,
-         PMD_SECT_OUTER_SHARE | PMD_SECT_NS },
+         PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS },
 #elif defined(CONFIG_FSL_LSCH2)
        { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
          CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE,
-         PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
+         PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
        { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
-         CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE },
+         CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PTE_BLOCK_NON_SHARE },
        { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
          CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE,
-         PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
+         PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
        { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE,
-         CONFIG_SYS_FSL_QSPI_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+         CONFIG_SYS_FSL_QSPI_SIZE, MT_DEVICE_NGNRNE, PTE_BLOCK_NON_SHARE },
        { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
-         CONFIG_SYS_FSL_IFC_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+         CONFIG_SYS_FSL_IFC_SIZE, MT_DEVICE_NGNRNE, PTE_BLOCK_NON_SHARE },
        { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
-         CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, PMD_SECT_OUTER_SHARE },
+         CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, PTE_BLOCK_OUTER_SHARE },
        { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
-         CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE },
+         CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PTE_BLOCK_OUTER_SHARE },
 #endif
 };
 
@@ -166,96 +166,96 @@ static const struct sys_mmu_table final_mmu_table[] = {
 #ifdef CONFIG_FSL_LSCH3
        { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
          CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE,
-         PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
+         PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
        { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
-         CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE },
+         CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PTE_BLOCK_NON_SHARE },
        { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
          CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL,
-         PMD_SECT_OUTER_SHARE | PMD_SECT_NS },
+         PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS },
        { CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2,
          CONFIG_SYS_FSL_QSPI_SIZE2, MT_DEVICE_NGNRNE,
-         PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
+         PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
        { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
-         CONFIG_SYS_FSL_IFC_SIZE2, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+         CONFIG_SYS_FSL_IFC_SIZE2, MT_DEVICE_NGNRNE, PTE_BLOCK_NON_SHARE },
        { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
          CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE,
-         PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
+         PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
        { CONFIG_SYS_FSL_MC_BASE, CONFIG_SYS_FSL_MC_BASE,
          CONFIG_SYS_FSL_MC_SIZE, MT_DEVICE_NGNRNE,
-         PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
+         PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
        { CONFIG_SYS_FSL_NI_BASE, CONFIG_SYS_FSL_NI_BASE,
          CONFIG_SYS_FSL_NI_SIZE, MT_DEVICE_NGNRNE,
-         PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
+         PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
        /* For QBMAN portal, only the first 64MB is cache-enabled */
        { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
          CONFIG_SYS_FSL_QBMAN_SIZE_1, MT_NORMAL,
-         PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN | PMD_SECT_NS },
+         PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN | PTE_BLOCK_NS },
        { CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
          CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
          CONFIG_SYS_FSL_QBMAN_SIZE - CONFIG_SYS_FSL_QBMAN_SIZE_1,
-         MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
+         MT_DEVICE_NGNRNE, PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
        { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
          CONFIG_SYS_PCIE1_PHYS_SIZE, MT_DEVICE_NGNRNE,
-         PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
+         PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
        { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
          CONFIG_SYS_PCIE2_PHYS_SIZE, MT_DEVICE_NGNRNE,
-         PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
+         PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
        { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
          CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE,
-         PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
+         PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
 #if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
        { CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR,
          CONFIG_SYS_PCIE4_PHYS_SIZE, MT_DEVICE_NGNRNE,
-         PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
+         PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
 #endif
        { CONFIG_SYS_FSL_WRIOP1_BASE, CONFIG_SYS_FSL_WRIOP1_BASE,
          CONFIG_SYS_FSL_WRIOP1_SIZE, MT_DEVICE_NGNRNE,
-         PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
+         PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
        { CONFIG_SYS_FSL_AIOP1_BASE, CONFIG_SYS_FSL_AIOP1_BASE,
          CONFIG_SYS_FSL_AIOP1_SIZE, MT_DEVICE_NGNRNE,
-         PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
+         PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
        { CONFIG_SYS_FSL_PEBUF_BASE, CONFIG_SYS_FSL_PEBUF_BASE,
          CONFIG_SYS_FSL_PEBUF_SIZE, MT_DEVICE_NGNRNE,
-         PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
+         PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
        { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
          CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL,
-         PMD_SECT_OUTER_SHARE | PMD_SECT_NS },
+         PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS },
 #elif defined(CONFIG_FSL_LSCH2)
        { CONFIG_SYS_FSL_BOOTROM_BASE, CONFIG_SYS_FSL_BOOTROM_BASE,
          CONFIG_SYS_FSL_BOOTROM_SIZE, MT_DEVICE_NGNRNE,
-         PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
+         PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
        { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
          CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE,
-         PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
+         PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
        { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
-         CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE },
+         CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PTE_BLOCK_NON_SHARE },
        { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
          CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE,
-         PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
+         PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
        { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE,
          CONFIG_SYS_FSL_QSPI_SIZE, MT_DEVICE_NGNRNE,
-         PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
+         PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
        { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
-         CONFIG_SYS_FSL_IFC_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+         CONFIG_SYS_FSL_IFC_SIZE, MT_DEVICE_NGNRNE, PTE_BLOCK_NON_SHARE },
        { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
          CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL,
-         PMD_SECT_OUTER_SHARE | PMD_SECT_NS },
+         PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS },
        { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
          CONFIG_SYS_FSL_QBMAN_SIZE, MT_DEVICE_NGNRNE,
-         PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
+         PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
        { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
-         CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE },
+         CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PTE_BLOCK_OUTER_SHARE },
        { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
          CONFIG_SYS_PCIE1_PHYS_SIZE, MT_DEVICE_NGNRNE,
-         PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
+         PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
        { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
          CONFIG_SYS_PCIE2_PHYS_SIZE, MT_DEVICE_NGNRNE,
-         PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
+         PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
        { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
          CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE,
-         PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
+         PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
        { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
-         CONFIG_SYS_FSL_DRAM_SIZE3, MT_NORMAL, PMD_SECT_OUTER_SHARE },
+         CONFIG_SYS_FSL_DRAM_SIZE3, MT_NORMAL, PTE_BLOCK_OUTER_SHARE },
 #endif
 };
 #endif